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-rw-r--r--src/northbridge/amd/agesa/family14/state_machine.c4
-rw-r--r--src/southbridge/amd/cimx/sb800/Kconfig3
-rw-r--r--src/southbridge/amd/cimx/sb800/reset.c19
-rw-r--r--src/southbridge/amd/cimx/sb900/Kconfig3
-rw-r--r--src/southbridge/amd/cimx/sb900/reset.c19
5 files changed, 14 insertions, 34 deletions
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index fd9e3d0eaa..81ce57f13b 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -18,11 +18,11 @@
#include <arch/io.h>
#include <cbmem.h>
+#include <cf9_reset.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <halt.h>
-#include <reset.h>
#include <smp/node.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -46,7 +46,7 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
if (mct_cfg_lo & (1<<19)) {
printk(BIOS_CRIT, "C6DramLock is set, resetting\n");
- hard_reset();
+ system_reset();
}
}
}
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 07232f1a74..aa5160b68f 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -19,7 +19,8 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select AMD_SB_CIMX
- select HAVE_HARD_RESET
+ select HAVE_CF9_RESET
+ select HAVE_CF9_RESET_PREPARE
if SOUTHBRIDGE_AMD_CIMX_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index 40e861c215..b7ee613428 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <cf9_reset.h>
#include <reset.h>
#define HT_INIT_CONTROL 0x6C
@@ -24,7 +25,7 @@
#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-static inline void set_bios_reset(void)
+void cf9_reset_prepare(void)
{
u32 nodes;
u32 htic;
@@ -40,19 +41,7 @@ static inline void set_bios_reset(void)
}
}
-void do_hard_reset(void)
+void do_board_reset(void)
{
- set_bios_reset();
- /* Try rebooting through port 0xcf9 */
- /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
- outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
-
-//SbReset();
-void do_soft_reset(void)
-{
- set_bios_reset();
- /* link reset */
- outb(0x06, 0x0cf9);
+ system_reset();
}
diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig
index 1fab6a7ec2..be3b16dd58 100644
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -18,7 +18,8 @@ config SOUTHBRIDGE_AMD_CIMX_SB900
default n
select IOAPIC
select AMD_SB_CIMX
- select HAVE_HARD_RESET
+ select HAVE_CF9_RESET
+ select HAVE_CF9_RESET_PREPARE
if SOUTHBRIDGE_AMD_CIMX_SB900
config SATA_CONTROLLER_MODE
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index 40e861c215..b7ee613428 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <cf9_reset.h>
#include <reset.h>
#define HT_INIT_CONTROL 0x6C
@@ -24,7 +25,7 @@
#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-static inline void set_bios_reset(void)
+void cf9_reset_prepare(void)
{
u32 nodes;
u32 htic;
@@ -40,19 +41,7 @@ static inline void set_bios_reset(void)
}
}
-void do_hard_reset(void)
+void do_board_reset(void)
{
- set_bios_reset();
- /* Try rebooting through port 0xcf9 */
- /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
- outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
-
-//SbReset();
-void do_soft_reset(void)
-{
- set_bios_reset();
- /* link reset */
- outb(0x06, 0x0cf9);
+ system_reset();
}