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-rw-r--r--src/drivers/generic/bayhub/bh720.c26
-rw-r--r--src/mainboard/google/kahlee/mainboard.c7
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h6
3 files changed, 33 insertions, 6 deletions
diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c
index 3a0a9721ad..3e78b4f049 100644
--- a/src/drivers/generic/bayhub/bh720.c
+++ b/src/drivers/generic/bayhub/bh720.c
@@ -24,16 +24,24 @@
enum {
BH720_PROTECT = 0xd0,
+ BH720_PROTECT_LOCK_OFF = 0,
+ BH720_PROTECT_LOCK_ON = BIT(0),
BH720_PROTECT_OFF = 0,
- BH720_PROTECT_ON = 1,
-
- BH720_RTD3_L1 = 0x3e0,
- BH720_RTD3_L1_DISABLE_L1 = BIT(28),
+ BH720_PROTECT_ON = BIT(31),
BH720_LINK_CTRL = 0x90,
BH720_LINK_CTRL_L0_ENABLE = BIT(0),
BH720_LINK_CTRL_L1_ENABLE = BIT(1),
BH720_LINK_CTRL_CLKREQ = BIT(8),
+
+ BH720_MISC2 = 0xf0,
+ BH720_MISC2_ASPM_DISABLE = BIT(0),
+ BH720_MISC2_APSM_CLKREQ_L1 = BIT(7),
+ BH720_MISC2_APSM_PHY_L1 = BIT(10),
+ BH720_MISC2_APSM_MORE = BIT(12),
+
+ BH720_RTD3_L1 = 0x3e0,
+ BH720_RTD3_L1_DISABLE_L1 = BIT(28),
};
static void bh720_init(struct device *dev)
@@ -47,13 +55,19 @@ static void bh720_init(struct device *dev)
* This procedure for enabling power-saving mode is from the
* BayHub BIOS Implementation Guideline document.
*/
- pci_write_config32(dev, BH720_PROTECT, BH720_PROTECT_OFF);
+ pci_write_config32(dev, BH720_PROTECT,
+ BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1);
pci_or_config32(dev, BH720_LINK_CTRL,
BH720_LINK_CTRL_L0_ENABLE |
BH720_LINK_CTRL_L1_ENABLE);
pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ);
- pci_write_config32(dev, BH720_PROTECT, BH720_PROTECT_ON);
+ pci_update_config32(dev, BH720_MISC2, ~BH720_MISC2_ASPM_DISABLE,
+ BH720_MISC2_APSM_CLKREQ_L1 |
+ BH720_MISC2_APSM_PHY_L1);
+ pci_write_config32(dev, BH720_PROTECT,
+ BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
+
printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
pci_read_config32(dev, BH720_LINK_CTRL));
}
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 6ba69a3665..cf600d2cec 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <arch/acpi.h>
+#include <arch/io.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/amd_pci_util.h>
#include <cbmem.h>
@@ -143,6 +144,12 @@ static void mainboard_init(void *chip_info)
/* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
+
+ /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
+ clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
+ GPP_CLK2_CLOCK_REQ_MAP_MASK,
+ GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
+ GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
}
/*************************************************
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 77e4979698..3e70c32c25 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -356,6 +356,12 @@
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
+/* Bit definitions for MISC_MMIO_BASE register GPPClkCntrl */
+#define GPP_CLK_CNTRL 0
+#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8
+#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
+#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3
+
struct stoneyridge_aoac {
int enable;
int status;