diff options
| -rw-r--r-- | src/ec/google/chromeec/Kconfig | 6 | ||||
| -rw-r--r-- | src/ec/google/chromeec/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/ec/google/chromeec/ec.h | 7 | ||||
| -rw-r--r-- | src/ec/google/chromeec/ec_lpc.c | 16 | ||||
| -rw-r--r-- | src/ec/google/chromeec/ec_mec.c | 105 |
5 files changed, 138 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 48a92d9793..25cc0e4b24 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -41,6 +41,12 @@ config EC_GOOGLE_CHROMEEC_LPC help Google Chrome EC via LPC bus. +config EC_GOOGLE_CHROMEEC_MEC + depends on EC_GOOGLE_CHROMEEC_LPC + def_bool n + help + Microchip EC variant for LPC register access. + config EC_GOOGLE_CHROMEEC_SPI depends on EC_GOOGLE_CHROMEEC def_bool n diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 0df6e8b1c5..8757c0b594 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,19 +1,23 @@ ramstage-y += ec.c crosec_proto.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c smm-y += ec.c crosec_proto.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +smm-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c romstage-y += ec.c crosec_proto.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y) verstage-y += ec.c crosec_proto.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c endif diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index cdf94dae16..a0acd178bf 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -54,6 +54,13 @@ void google_chromeec_post(u8 postcode); void google_chromeec_log_events(u32 mask); int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len); +/* For MEC, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */ +#define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0 +#define MEC_EMI_RANGE_END (EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SIZE) + +void mec_io_bytes(int write, u16 offset, unsigned int length, + u8 *buf, u8 *csum); + enum usb_charge_mode { USB_CHARGE_MODE_DISABLED, USB_CHARGE_MODE_CHARGE_AUTO, diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 0fa0cf8d6d..826142bcf1 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -41,6 +41,14 @@ static void read_bytes(u16 port, unsigned int length, u8 *dest, u8 *csum) { int i; +#if CONFIG_EC_GOOGLE_CHROMEEC_MEC + /* Access desired range though EMI interface */ + if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { + mec_io_bytes(0, port, length, dest, csum); + return; + } +#endif + for (i = 0; i < length; ++i) { dest[i] = inb(port + i); if (csum) @@ -68,6 +76,14 @@ static void write_bytes(u16 port, unsigned int length, u8 *msg, u8 *csum) { int i; +#if CONFIG_EC_GOOGLE_CHROMEEC_MEC + /* Access desired range though EMI interface */ + if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) { + mec_io_bytes(1, port, length, msg, csum); + return; + } +#endif + for (i = 0; i < length; ++i) { outb(msg[i], port + i); if (csum) diff --git a/src/ec/google/chromeec/ec_mec.c b/src/ec/google/chromeec/ec_mec.c new file mode 100644 index 0000000000..9836edad67 --- /dev/null +++ b/src/ec/google/chromeec/ec_mec.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include "ec.h" +#include "ec_commands.h" + +enum { + /* 8-bit access */ + ACCESS_TYPE_BYTE = 0x0, + /* 16-bit access */ + ACCESS_TYPE_WORD = 0x1, + /* 32-bit access */ + ACCESS_TYPE_LONG = 0x2, + /* + * 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the + * EC data register to be incremented. + */ + ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3, +}; + +/* EMI registers are relative to base */ +#define MEC_EMI_BASE 0x800 +#define MEC_EMI_HOST_TO_EC (MEC_EMI_BASE + 0) +#define MEC_EMI_EC_TO_HOST (MEC_EMI_BASE + 1) +#define MEC_EMI_EC_ADDRESS_B0 (MEC_EMI_BASE + 2) +#define MEC_EMI_EC_ADDRESS_B1 (MEC_EMI_BASE + 3) +#define MEC_EMI_EC_DATA_B0 (MEC_EMI_BASE + 4) +#define MEC_EMI_EC_DATA_B1 (MEC_EMI_BASE + 5) +#define MEC_EMI_EC_DATA_B2 (MEC_EMI_BASE + 6) +#define MEC_EMI_EC_DATA_B3 (MEC_EMI_BASE + 7) + +/* + * cros_ec_lpc_mec_emi_write_address + * + * Initialize EMI read / write at a given address. + * + * @addr: Starting read / write address + * @access_mode: Type of access, typically 32-bit auto-increment + */ +static void mec_emi_write_address(u16 addr, u8 access_mode) +{ + /* Address relative to start of EMI range */ + addr -= MEC_EMI_RANGE_START; + outb((addr & 0xfc) | access_mode, MEC_EMI_EC_ADDRESS_B0); + outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1); +} + +/* + * mec_io_bytes - Read / write bytes to MEC EMI port + * + * @write: 1 on write operation, 0 on read + * @port: Base read / write address + * @length: Number of bytes to read / write + * @buf: Destination / source buffer + * @csum: Optional parameter, sums data transferred + * + */ +void mec_io_bytes(int write, u16 port, unsigned int length, u8 *buf, u8 *csum) +{ + int i = 0; + int io_addr; + + if (length == 0) + return; + + /* Initialize I/O at desired address */ + mec_emi_write_address(port, ACCESS_TYPE_LONG_AUTO_INCREMENT); + + /* Skip bytes in case of misaligned port */ + io_addr = MEC_EMI_EC_DATA_B0 + (port & 0x3); + while (i < length) { + while (io_addr <= MEC_EMI_EC_DATA_B3) { + if (write) + outb(buf[i], io_addr++); + else + buf[i] = inb(io_addr++); + if (csum) + *csum += buf[i]; + + /* Extra bounds check in case of misaligned length */ + if (++i == length) + return; + } + + /* Access [B0, B3] on each loop pass */ + io_addr = MEC_EMI_EC_DATA_B0; + } +} |