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-rw-r--r--src/soc/amd/stoneyridge/enable_usbdebug.c17
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h5
2 files changed, 12 insertions, 10 deletions
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index efe34e5141..81f60f0e9a 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -22,8 +22,6 @@
#include <device/pci_def.h>
#include <soc/southbridge.h>
-#define DEBUGPORT_MISC_CONTROL 0x80
-
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
/* Enable all of the USB controllers */
@@ -40,13 +38,12 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
- u8 *base_regs = pci_ehci_base_regs(dev);
- u32 reg32;
+ u32 reg32, value;
- /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
- reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
- reg32 &= ~(0xf << 28);
- reg32 |= (port << 28);
- reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
- write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+ value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT;
+ value |= DEBUG_PORT_ENABLE;
+ reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4);
+ reg32 &= ~DEBUG_PORT_MASK;
+ reg32 |= value;
+ pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32);
}
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 530b93a3e4..f054b3b61e 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -305,6 +305,11 @@
#define OC_PORT2_SHIFT 8
#define OC_PORT3_SHIFT 12
+#define EHCI_HUB_CONFIG4 0x90
+#define DEBUG_PORT_SELECT_SHIFT 16
+#define DEBUG_PORT_ENABLE BIT(18)
+#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))
+
#define WIDEIO_RANGE_ERROR -1
#define TOTAL_WIDEIO_PORTS 3