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-rw-r--r--src/mainboard/google/kahlee/mainboard.c1
-rw-r--r--src/soc/amd/common/block/acpi/halt.c1
-rw-r--r--src/soc/amd/common/block/acpimmio/Kconfig6
-rw-r--r--src/soc/amd/common/block/acpimmio/Makefile.inc6
-rw-r--r--src/soc/amd/common/block/acpimmio/mmio_util.c379
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio.h101
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio_map.h67
-rw-r--r--src/soc/amd/stoneyridge/Kconfig1
-rw-r--r--src/soc/amd/stoneyridge/acpi.c1
-rw-r--r--src/soc/amd/stoneyridge/gpio.c4
-rw-r--r--src/soc/amd/stoneyridge/include/soc/iomap.h29
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h59
-rw-r--r--src/soc/amd/stoneyridge/lpc.c1
-rw-r--r--src/soc/amd/stoneyridge/pmutil.c1
-rw-r--r--src/soc/amd/stoneyridge/ramtop.c3
-rw-r--r--src/soc/amd/stoneyridge/reset.c1
-rw-r--r--src/soc/amd/stoneyridge/sb_util.c351
-rw-r--r--src/soc/amd/stoneyridge/smbus.c1
-rw-r--r--src/soc/amd/stoneyridge/smi.c1
-rw-r--r--src/soc/amd/stoneyridge/smi_util.c1
-rw-r--r--src/soc/amd/stoneyridge/smihandler.c1
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c13
-rw-r--r--src/soc/amd/stoneyridge/usb.c2
23 files changed, 582 insertions, 449 deletions
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index ad979a567f..cfd5637633 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -27,6 +27,7 @@
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
#include <variant/ec.h>
#include <variant/thermal.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/soc/amd/common/block/acpi/halt.c b/src/soc/amd/common/block/acpi/halt.c
index 8f36efb042..200b3c12f5 100644
--- a/src/soc/amd/common/block/acpi/halt.c
+++ b/src/soc/amd/common/block/acpi/halt.c
@@ -15,6 +15,7 @@
#include <arch/acpi.h>
#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
#include <halt.h>
void poweroff(void)
diff --git a/src/soc/amd/common/block/acpimmio/Kconfig b/src/soc/amd/common/block/acpimmio/Kconfig
new file mode 100644
index 0000000000..f14cc0c227
--- /dev/null
+++ b/src/soc/amd/common/block/acpimmio/Kconfig
@@ -0,0 +1,6 @@
+config SOC_AMD_COMMON_BLOCK_ACPIMMIO
+ bool
+ default n
+ help
+ Select this option to enable hardware blocks in the AcpiMmio
+ address space (0xfed8xxxx).
diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc
new file mode 100644
index 0000000000..9517b10b8a
--- /dev/null
+++ b/src/soc/amd/common/block/acpimmio/Makefile.inc
@@ -0,0 +1,6 @@
+bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
+verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
+postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c
diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
new file mode 100644
index 0000000000..7d4c4c5df1
--- /dev/null
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -0,0 +1,379 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <arch/io.h>
+#include <device/mmio.h>
+#include <amdblocks/acpimmio_map.h>
+#include <amdblocks/acpimmio.h>
+
+void enable_acpimmio_decode(void)
+{
+ uint32_t dw;
+
+ dw = pm_io_read32(ACPIMMIO_DECODE_REGISTER);
+ dw |= ACPIMMIO_DECODE_EN;
+ pm_io_write32(ACPIMMIO_DECODE_REGISTER, dw);
+}
+
+/* PM registers are accessed a byte at a time via CD6/CD7 */
+uint8_t pm_io_read8(uint8_t reg)
+{
+ outb(reg, PM_INDEX);
+ return inb(PM_DATA);
+}
+
+uint16_t pm_io_read16(uint8_t reg)
+{
+ return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg);
+}
+
+uint32_t pm_io_read32(uint8_t reg)
+{
+ return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg);
+}
+
+void pm_io_write8(uint8_t reg, uint8_t value)
+{
+ outb(reg, PM_INDEX);
+ outb(value, PM_DATA);
+}
+
+void pm_io_write16(uint8_t reg, uint16_t value)
+{
+ pm_io_write8(reg, value & 0xff);
+ value >>= 8;
+ pm_io_write8(reg + sizeof(uint8_t), value & 0xff);
+}
+
+void pm_io_write32(uint8_t reg, uint32_t value)
+{
+ pm_io_write16(reg, value & 0xffff);
+ value >>= 16;
+ pm_io_write16(reg + sizeof(uint16_t), value & 0xffff);
+}
+
+/* smbus pci read/write - access registers at 0xfed80000 - currently unused */
+
+/* smi read/write - access registers at 0xfed80200 */
+
+uint8_t smi_read8(uint8_t offset)
+{
+ return read8((void *)(ACPIMMIO_SMI_BASE + offset));
+}
+
+uint16_t smi_read16(uint8_t offset)
+{
+ return read16((void *)(ACPIMMIO_SMI_BASE + offset));
+}
+
+uint32_t smi_read32(uint8_t offset)
+{
+ return read32((void *)(ACPIMMIO_SMI_BASE + offset));
+}
+
+void smi_write8(uint8_t offset, uint8_t value)
+{
+ write8((void *)(ACPIMMIO_SMI_BASE + offset), value);
+}
+
+void smi_write16(uint8_t offset, uint16_t value)
+{
+ write16((void *)(ACPIMMIO_SMI_BASE + offset), value);
+}
+
+void smi_write32(uint8_t offset, uint32_t value)
+{
+ write32((void *)(ACPIMMIO_SMI_BASE + offset), value);
+}
+
+/* pm read/write - access registers at 0xfed80300 */
+
+u8 pm_read8(u8 reg)
+{
+ return read8((void *)(ACPIMMIO_PMIO_BASE + reg));
+}
+
+u16 pm_read16(u8 reg)
+{
+ return read16((void *)(ACPIMMIO_PMIO_BASE + reg));
+}
+
+u32 pm_read32(u8 reg)
+{
+ return read32((void *)(ACPIMMIO_PMIO_BASE + reg));
+}
+
+void pm_write8(u8 reg, u8 value)
+{
+ write8((void *)(ACPIMMIO_PMIO_BASE + reg), value);
+}
+
+void pm_write16(u8 reg, u16 value)
+{
+ write16((void *)(ACPIMMIO_PMIO_BASE + reg), value);
+}
+
+void pm_write32(u8 reg, u32 value)
+{
+ write32((void *)(ACPIMMIO_PMIO_BASE + reg), value);
+}
+
+/* pm2 read/write - access registers at 0xfed80400 - currently unused */
+
+/* biosram read/write - access registers at 0xfed80500 */
+
+uint8_t biosram_read8(uint8_t offset)
+{
+ return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset));
+}
+
+uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */
+{
+ int i;
+ uint16_t value = 0;
+ for (i = sizeof(value) - 1 ; i >= 0 ; i--)
+ value = (value << 8) | biosram_read8(offset + i);
+ return value;
+}
+
+uint32_t biosram_read32(uint8_t offset)
+{
+ uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16;
+ return value | biosram_read16(offset);
+}
+
+void biosram_write8(uint8_t offset, uint8_t value)
+{
+ write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value);
+}
+
+void biosram_write16(uint8_t offset, uint16_t value)
+{
+ int i;
+ for (i = 0 ; i < sizeof(value) ; i++) {
+ biosram_write8(offset + i, value & 0xff);
+ value >>= 8;
+ }
+}
+
+void biosram_write32(uint8_t offset, uint32_t value)
+{
+ int i;
+ for (i = 0 ; i < sizeof(value) ; i++) {
+ biosram_write8(offset + i, value & 0xff);
+ value >>= 8;
+ }
+}
+
+/* cmosram read/write - access registers at 0xfed80600 - currently unused */
+
+/* cmos read/write - access registers at 0xfed80700 - currently unused */
+
+/* acpi read/write - access registers at 0xfed80800 */
+
+u8 acpi_read8(u8 reg)
+{
+ return read8((void *)(ACPIMMIO_ACPI_BASE + reg));
+}
+
+u16 acpi_read16(u8 reg)
+{
+ return read16((void *)(ACPIMMIO_ACPI_BASE + reg));
+}
+
+u32 acpi_read32(u8 reg)
+{
+ return read32((void *)(ACPIMMIO_ACPI_BASE + reg));
+}
+
+void acpi_write8(u8 reg, u8 value)
+{
+ write8((void *)(ACPIMMIO_ACPI_BASE + reg), value);
+}
+
+void acpi_write16(u8 reg, u16 value)
+{
+ write16((void *)(ACPIMMIO_ACPI_BASE + reg), value);
+}
+
+void acpi_write32(u8 reg, u32 value)
+{
+ write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
+}
+
+/* asf read/write - access registers at 0xfed80900 - not currently used */
+
+u8 asf_read8(u8 reg)
+{
+ return read8((void *)(ACPIMMIO_ASF_BASE + reg));
+}
+
+u16 asf_read16(u8 reg)
+{
+ return read16((void *)(ACPIMMIO_ASF_BASE + reg));
+}
+
+void asf_write8(u8 reg, u8 value)
+{
+ write8((void *)(ACPIMMIO_ASF_BASE + reg), value);
+}
+
+void asf_write16(u8 reg, u16 value)
+{
+ write16((void *)(ACPIMMIO_ASF_BASE + reg), value);
+}
+
+/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */
+
+u8 smbus_read8(u8 reg)
+{
+ return read8((void *)(ACPIMMIO_SMBUS_BASE + reg));
+}
+
+u16 smbus_read16(u8 reg)
+{
+ return read16((void *)(ACPIMMIO_SMBUS_BASE + reg));
+}
+
+void smbus_write8(u8 reg, u8 value)
+{
+ write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
+}
+
+void smbus_write16(u8 reg, u16 value)
+{
+ write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
+}
+
+/* wdt read/write - access registers at 0xfed80b00 - not currently used */
+
+/* hpet read/write - access registers at 0xfed80c00 - not currently used */
+
+/* iomux read/write - access registers at 0xfed80d00 */
+
+u8 iomux_read8(u8 reg)
+{
+ return read8((void *)(ACPIMMIO_IOMUX_BASE + reg));
+}
+
+u16 iomux_read16(u8 reg)
+{
+ return read16((void *)(ACPIMMIO_IOMUX_BASE + reg));
+}
+
+u32 iomux_read32(u8 reg)
+{
+ return read32((void *)(ACPIMMIO_IOMUX_BASE + reg));
+}
+
+void iomux_write8(u8 reg, u8 value)
+{
+ write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
+}
+
+void iomux_write16(u8 reg, u16 value)
+{
+ write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
+}
+
+void iomux_write32(u8 reg, u32 value)
+{
+ write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
+}
+
+/* misc read/write - access registers at 0xfed80e00 */
+
+u8 misc_read8(u8 reg)
+{
+ return read8((void *)(ACPIMMIO_MISC_BASE + reg));
+}
+
+u16 misc_read16(u8 reg)
+{
+ return read16((void *)(ACPIMMIO_MISC_BASE + reg));
+}
+
+u32 misc_read32(u8 reg)
+{
+ return read32((void *)(ACPIMMIO_MISC_BASE + reg));
+}
+
+void misc_write8(u8 reg, u8 value)
+{
+ write8((void *)(ACPIMMIO_MISC_BASE + reg), value);
+}
+
+void misc_write16(u8 reg, u16 value)
+{
+ write16((void *)(ACPIMMIO_MISC_BASE + reg), value);
+}
+
+void misc_write32(u8 reg, u32 value)
+{
+ write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
+}
+
+/* dpvga read/write - access registers at 0xfed81400 - not currently used */
+
+/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */
+/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */
+/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */
+
+/* xhci_pm read/write - access registers at 0xfed81c00 */
+
+uint8_t xhci_pm_read8(uint8_t reg)
+{
+ return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg));
+}
+
+uint16_t xhci_pm_read16(uint8_t reg)
+{
+ return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg));
+}
+
+uint32_t xhci_pm_read32(uint8_t reg)
+{
+ return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg));
+}
+
+void xhci_pm_write8(uint8_t reg, uint8_t value)
+{
+ write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
+}
+
+void xhci_pm_write16(uint8_t reg, uint16_t value)
+{
+ write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
+}
+
+void xhci_pm_write32(uint8_t reg, uint32_t value)
+{
+ write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
+}
+
+/* acdc_tmr read/write - access registers at 0xfed81d00 */
+
+/* aoac read/write - access registers at 0xfed81e00 - not currently used */
+
+u8 aoac_read8(u8 reg)
+{
+ return read8((void *)(ACPIMMIO_AOAC_BASE + reg));
+}
+
+void aoac_write8(u8 reg, u8 value)
+{
+ write8((void *)(ACPIMMIO_AOAC_BASE + reg), value);
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
new file mode 100644
index 0000000000..e1cf7cbdc2
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMDBLOCKS_ACPIMMIO_H__
+#define __AMDBLOCKS_ACPIMMIO_H__
+
+void enable_acpimmio_decode(void);
+uint8_t pm_io_read8(uint8_t reg);
+uint16_t pm_io_read16(uint8_t reg);
+uint32_t pm_io_read32(uint8_t reg);
+void pm_io_write8(uint8_t reg, uint8_t value);
+void pm_io_write16(uint8_t reg, uint16_t value);
+void pm_io_write32(uint8_t reg, uint32_t value);
+uint8_t smi_read8(uint8_t offset);
+uint16_t smi_read16(uint8_t offset);
+uint32_t smi_read32(uint8_t offset);
+void smi_write8(uint8_t offset, uint8_t value);
+void smi_write16(uint8_t offset, uint16_t value);
+void smi_write32(uint8_t offset, uint32_t value);
+uint8_t pm_read8(uint8_t reg);
+uint16_t pm_read16(uint8_t reg);
+uint32_t pm_read32(uint8_t reg);
+void pm_write8(uint8_t reg, uint8_t value);
+void pm_write16(uint8_t reg, uint16_t value);
+void pm_write32(uint8_t reg, uint32_t value);
+uint8_t pm2_read8(uint8_t reg);
+uint16_t pm2_read16(uint8_t reg);
+uint32_t pm2_read32(uint8_t reg);
+void pm2_write8(uint8_t reg, uint8_t value);
+void pm2_write16(uint8_t reg, uint16_t value);
+void pm2_write32(uint8_t reg, uint32_t value);
+uint8_t biosram_read8(uint8_t offset);
+void biosram_write8(uint8_t offset, uint8_t value);
+uint16_t biosram_read16(uint8_t offset);
+uint32_t biosram_read32(uint8_t offset);
+void biosram_write16(uint8_t offset, uint16_t value);
+void biosram_write32(uint8_t offset, uint32_t value);
+uint8_t acpi_read8(uint8_t reg);
+uint16_t acpi_read16(uint8_t reg);
+uint32_t acpi_read32(uint8_t reg);
+void acpi_write8(uint8_t reg, uint8_t value);
+void acpi_write16(uint8_t reg, uint16_t value);
+void acpi_write32(uint8_t reg, uint32_t value);
+uint8_t asf_read8(uint8_t reg);
+uint16_t asf_read16(uint8_t reg);
+uint32_t asf_read32(uint8_t reg);
+void asf_write8(uint8_t reg, uint8_t value);
+void asf_write16(uint8_t reg, uint16_t value);
+void asf_write32(uint8_t reg, uint32_t value);
+uint8_t smbus_read8(uint8_t reg);
+uint16_t smbus_read16(uint8_t reg);
+void smbus_write8(uint8_t reg, uint8_t value);
+void smbus_write16(uint8_t reg, uint16_t value);
+uint8_t wdt_read8(uint8_t reg);
+uint16_t wdt_read16(uint8_t reg);
+uint32_t wdt_read32(uint8_t reg);
+void wdt_write8(uint8_t reg, uint8_t value);
+void wdt_write16(uint8_t reg, uint16_t value);
+void wdt_write32(uint8_t reg, uint32_t value);
+uint8_t hpet_read8(uint8_t reg);
+uint16_t hpet_read16(uint8_t reg);
+uint32_t hpet_read32(uint8_t reg);
+void hpet_write8(uint8_t reg, uint8_t value);
+void hpet_write16(uint8_t reg, uint16_t value);
+void hpet_write32(uint8_t reg, uint32_t value);
+uint8_t iomux_read8(uint8_t reg);
+uint16_t iomux_read16(uint8_t reg);
+uint32_t iomux_read32(uint8_t reg);
+void iomux_write8(uint8_t reg, uint8_t value);
+void iomux_write16(uint8_t reg, uint16_t value);
+void iomux_write32(uint8_t reg, uint32_t value);
+uint8_t misc_read8(uint8_t reg);
+uint16_t misc_read16(uint8_t reg);
+uint32_t misc_read32(uint8_t reg);
+void misc_write8(uint8_t reg, uint8_t value);
+void misc_write16(uint8_t reg, uint16_t value);
+void misc_write32(uint8_t reg, uint32_t value);
+uint8_t xhci_pm_read8(uint8_t reg);
+uint16_t xhci_pm_read16(uint8_t reg);
+uint32_t xhci_pm_read32(uint8_t reg);
+void xhci_pm_write8(uint8_t reg, uint8_t value);
+void xhci_pm_write16(uint8_t reg, uint16_t value);
+void xhci_pm_write32(uint8_t reg, uint32_t value);
+uint8_t aoac_read8(uint8_t reg);
+void aoac_write8(uint8_t reg, uint8_t value);
+
+#endif /* __AMDBLOCKS_ACPIMMIO_H__ */
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
new file mode 100644
index 0000000000..755af52d4f
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMDBLOCKS_ACPIMMIO_MAP_H__
+#define __AMDBLOCKS_ACPIMMIO_MAP_H__
+
+/* IO index/data for accessing PMIO prior to enabling MMIO decode */
+#define PM_INDEX 0xcd6
+#define PM_DATA 0xcd7
+
+/* TODO: In the event this is ported backward far enough, earlier devices
+ * enable the decode in PMx24 instead. All discrete FCHs and the Kabini
+ * SoC fall into this category. Kabini's successor, Mullins, uses this
+ * newer method.
+ */
+#define ACPIMMIO_DECODE_REGISTER 0x4
+#define ACPIMMIO_DECODE_EN BIT(0)
+
+/* MMIO register blocks are at fixed offsets from 0xfed80000 and are enabled
+ * in PMx24[1] (older implementations) and PMx04[1] (newer implementations).
+ * PM registers are also accessible via IO CD6/CD7.
+ *
+ * All products do not support all blocks below, however AMD has avoided
+ * redefining addresses and consumes new ranges as necessary.
+ *
+ * Definitions within each block are not guaranteed to remain consistent
+ * across family/model products.
+ */
+
+#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
+#define ACPIMMIO_SM_PCI_BASE 0xfed80000
+#define ACPIMMIO_SMI_BASE 0xfed80200
+#define ACPIMMIO_PMIO_BASE 0xfed80300
+#define ACPIMMIO_PMIO2_BASE 0xfed80400
+#define ACPIMMIO_BIOSRAM_BASE 0xfed80500
+#define ACPIMMIO_CMOSRAM_BASE 0xfed80600
+#define ACPIMMIO_CMOS_BASE 0xfed80700
+#define ACPIMMIO_ACPI_BASE 0xfed80800
+#define ACPIMMIO_ASF_BASE 0xfed80900
+#define ACPIMMIO_SMBUS_BASE 0xfed80a00
+#define ACPIMMIO_WDT_BASE 0xfed80b00
+#define ACPIMMIO_HPET_BASE 0xfed80c00
+#define ACPIMMIO_IOMUX_BASE 0xfed80d00
+#define ACPIMMIO_MISC_BASE 0xfed80e00
+#define ACPIMMIO_DPVGA_BASE 0xfed81400
+#define ACPIMMIO_GPIO0_BASE 0xfed81500
+#define ACPIMMIO_GPIO1_BASE 0xfed81600
+#define ACPIMMIO_GPIO2_BASE 0xfed81700
+#define ACPIMMIO_XHCIPM_BASE 0xfed81c00
+#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00
+#define ACPIMMIO_AOAC_BASE 0xfed81e00
+
+#endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 29ab149df9..d4e1feb251 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_PI
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
+ select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PI
select SOC_AMD_COMMON_BLOCK_PSP
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 227fb70136..4f11ea227a 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -28,6 +28,7 @@
#include <cbmem.h>
#include <device/device.h>
#include <device/pci.h>
+#include <amdblocks/acpimmio.h>
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index 285fedd238..01ced0880b 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -16,13 +16,15 @@
*/
#include <device/mmio.h>
+#include <device/device.h>
#include <console/console.h>
#include <delay.h>
#include <gpio.h>
+#include <amdblocks/acpimmio.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
-#include <soc/southbridge.h>
#include <assert.h>
+#include "chip.h"
static const struct soc_amd_event gpio_event_table[] = {
{ GPIO_1, GEVENT_19 },
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index e6327dc6db..7762043119 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -22,6 +22,9 @@
#define SPI_BASE_ADDRESS 0xfec10000
#define IO_APIC2_ADDR 0xfec20000
+/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */
+#include <amdblocks/acpimmio_map.h>
+
/* I2C fixed address */
#define I2C_BASE_ADDRESS 0xfedc2000
#define I2C_DEVICE_SIZE 0x00001000
@@ -32,30 +35,6 @@
#endif
#define HPET_BASE_ADDRESS 0xfed00000
-/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */
-#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000
-#define ACPIMMIO_SM_PCI_BASE 0xfed80000
-#define ACPIMMIO_SMI_BASE 0xfed80200
-#define ACPIMMIO_PMIO_BASE 0xfed80300
-#define ACPIMMIO_PMIO2_BASE 0xfed80400
-#define ACPIMMIO_BIOSRAM_BASE 0xfed80500
-#define ACPIMMIO_CMOSRAM_BASE 0xfed80600
-#define ACPIMMIO_CMOS_BASE 0xfed80700
-#define ACPIMMIO_ACPI_BASE 0xfed80800
-#define ACPIMMIO_ASF_BASE 0xfed80900
-#define ACPIMMIO_SMBUS_BASE 0xfed80a00
-#define ACPIMMIO_WDT_BASE 0xfed80b00
-#define ACPIMMIO_HPET_BASE 0xfed80c00
-#define ACPIMMIO_IOMUX_BASE 0xfed80d00
-#define ACPIMMIO_MISC_BASE 0xfed80e00
-#define ACPIMMIO_DPVGA_BASE 0xfed81400
-#define ACPIMMIO_GPIO0_BASE 0xfed81500
-#define ACPIMMIO_GPIO1_BASE 0xfed81600
-#define ACPIMMIO_GPIO2_BASE 0xfed81700
-#define ACPIMMIO_XHCIPM_BASE 0xfed81c00
-#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00
-#define ACPIMMIO_AOAC_BASE 0xfed81e00
-
#define APU_UART0_BASE 0xfedc6000
#define APU_UART1_BASE 0xfedc8000
@@ -78,8 +57,6 @@
#define PM2_DATA 0xcd1
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
-#define PM_INDEX 0xcd6
-#define PM_DATA 0xcd7
#define AB_INDX 0xcd8
#define AB_DATA (AB_INDX+4)
#define SYS_RESET 0xcf9
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 618a5deff7..6734efb04d 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -483,7 +483,6 @@ void southbridge_final(void *chip_info);
void southbridge_init(void *chip_info);
void sb_lpc_port80(void);
void sb_lpc_decode(void);
-void sb_acpi_mmio_decode(void);
void sb_pci_port80(void);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
@@ -491,66 +490,8 @@ void sb_tpm_decode(void);
void sb_tpm_decode_spi(void);
void lpc_wideio_512_window(uint16_t base);
void lpc_wideio_16_window(uint16_t base);
-uint8_t pm_io_read8(uint8_t reg);
-uint16_t pm_io_read16(uint8_t reg);
-uint32_t pm_io_read32(uint8_t reg);
-void pm_io_write8(uint8_t reg, uint8_t value);
-void pm_io_write16(uint8_t reg, uint16_t value);
-void pm_io_write32(uint8_t reg, uint32_t value);
-u8 pm_read8(u8 reg);
-u16 pm_read16(u8 reg);
-u32 pm_read32(u8 reg);
-void pm_write8(u8 reg, u8 value);
-void pm_write16(u8 reg, u16 value);
-void pm_write32(u8 reg, u32 value);
-u8 acpi_read8(u8 reg);
-u16 acpi_read16(u8 reg);
-u32 acpi_read32(u8 reg);
-void acpi_write8(u8 reg, u8 value);
-void acpi_write16(u8 reg, u16 value);
-void acpi_write32(u8 reg, u32 value);
-u8 misc_read8(u8 reg);
-u16 misc_read16(u8 reg);
-u32 misc_read32(u8 reg);
-void misc_write8(u8 reg, u8 value);
-void misc_write16(u8 reg, u16 value);
-void misc_write32(u8 reg, u32 value);
-uint8_t smi_read8(uint8_t offset);
-uint16_t smi_read16(uint8_t offset);
-uint32_t smi_read32(uint8_t offset);
-void smi_write8(uint8_t offset, uint8_t value);
-void smi_write16(uint8_t offset, uint16_t value);
-void smi_write32(uint8_t offset, uint32_t value);
-uint8_t biosram_read8(uint8_t offset);
-void biosram_write8(uint8_t offset, uint8_t value);
-uint16_t biosram_read16(uint8_t offset);
-void biosram_write16(uint8_t offset, uint16_t value);
-uint32_t biosram_read32(uint8_t offset);
-void biosram_write32(uint8_t offset, uint32_t value);
uint16_t pm_acpi_pm_cnt_blk(void);
uint16_t pm_acpi_pm_evt_blk(void);
-void xhci_pm_write8(uint8_t reg, uint8_t value);
-uint8_t xhci_pm_read8(uint8_t reg);
-void xhci_pm_write16(uint8_t reg, uint16_t value);
-uint16_t xhci_pm_read16(uint8_t reg);
-void xhci_pm_write32(uint8_t reg, uint32_t value);
-uint32_t xhci_pm_read32(uint8_t reg);
-u8 iomux_read8(u8 reg);
-u16 iomux_read16(u8 reg);
-u32 iomux_read32(u8 reg);
-void iomux_write8(u8 reg, u8 value);
-void iomux_write16(u8 reg, u16 value);
-void iomux_write32(u8 reg, u32 value);
-uint8_t asf_read8(uint8_t offset);
-uint16_t asf_read16(uint8_t offset);
-void asf_write8(uint8_t offset, uint8_t value);
-void asf_write16(uint8_t offset, uint16_t value);
-uint8_t smbus_read8(uint8_t offset);
-uint16_t smbus_read16(uint8_t offset);
-void smbus_write8(uint8_t offset, uint8_t value);
-void smbus_write16(uint8_t offset, uint16_t value);
-uint8_t aoac_read8(uint8_t reg);
-void aoac_write8(uint8_t reg, uint8_t value);
void bootblock_fch_early_init(void);
void bootblock_fch_init(void);
/**
diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c
index a838146c84..3ace1fdce6 100644
--- a/src/soc/amd/stoneyridge/lpc.c
+++ b/src/soc/amd/stoneyridge/lpc.c
@@ -27,6 +27,7 @@
#include <arch/ioapic.h>
#include <pc80/i8254.h>
#include <pc80/i8259.h>
+#include <amdblocks/acpimmio.h>
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c
index bfb5f424ef..7367251193 100644
--- a/src/soc/amd/stoneyridge/pmutil.c
+++ b/src/soc/amd/stoneyridge/pmutil.c
@@ -15,6 +15,7 @@
#include <arch/acpi.h>
#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
#include <security/vboot/vboot_common.h>
#include <security/vboot/vbnv.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index f43fcf37ec..7c855bb1e1 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -25,7 +25,8 @@
#include <stage_cache.h>
#include <arch/bert_storage.h>
#include <soc/northbridge.h>
-#include <soc/southbridge.h>
+#include <soc/iomap.h>
+#include <amdblocks/acpimmio.h>
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c
index 34aa576a09..ec5ee910d9 100644
--- a/src/soc/amd/stoneyridge/reset.c
+++ b/src/soc/amd/stoneyridge/reset.c
@@ -20,6 +20,7 @@
#include <soc/pci_devs.h>
#include <device/pci_ops.h>
#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
#include <amdblocks/reset.h>
void set_warm_reset_flag(void)
diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c
index 524efc45ad..11bf73a723 100644
--- a/src/soc/amd/stoneyridge/sb_util.c
+++ b/src/soc/amd/stoneyridge/sb_util.c
@@ -16,358 +16,9 @@
#include <arch/io.h>
#include <device/mmio.h>
#include <arch/acpi.h>
+#include <amdblocks/acpimmio.h>
#include <soc/southbridge.h>
-/* PM registers are accessed a byte at a time via CD6/CD7 */
-uint8_t pm_io_read8(uint8_t reg)
-{
- outb(reg, PM_INDEX);
- return inb(PM_DATA);
-}
-
-uint16_t pm_io_read16(uint8_t reg)
-{
- return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg);
-}
-
-uint32_t pm_io_read32(uint8_t reg)
-{
- return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg);
-}
-
-void pm_io_write8(uint8_t reg, uint8_t value)
-{
- outb(reg, PM_INDEX);
- outb(value, PM_DATA);
-}
-
-void pm_io_write16(uint8_t reg, uint16_t value)
-{
- pm_io_write8(reg, value & 0xff);
- value >>= 8;
- pm_io_write8(reg + sizeof(uint8_t), value & 0xff);
-}
-
-void pm_io_write32(uint8_t reg, uint32_t value)
-{
- pm_io_write16(reg, value & 0xffff);
- value >>= 16;
- pm_io_write16(reg + sizeof(uint16_t), value & 0xffff);
-}
-
-/* smbus pci read/write - access registers at 0xfed80000 - currently unused */
-
-/* smi read/write - access registers at 0xfed80200 */
-
-uint8_t smi_read8(uint8_t offset)
-{
- return read8((void *)(ACPIMMIO_SMI_BASE + offset));
-}
-
-uint16_t smi_read16(uint8_t offset)
-{
- return read16((void *)(ACPIMMIO_SMI_BASE + offset));
-}
-
-uint32_t smi_read32(uint8_t offset)
-{
- return read32((void *)(ACPIMMIO_SMI_BASE + offset));
-}
-
-void smi_write8(uint8_t offset, uint8_t value)
-{
- write8((void *)(ACPIMMIO_SMI_BASE + offset), value);
-}
-
-void smi_write16(uint8_t offset, uint16_t value)
-{
- write16((void *)(ACPIMMIO_SMI_BASE + offset), value);
-}
-
-void smi_write32(uint8_t offset, uint32_t value)
-{
- write32((void *)(ACPIMMIO_SMI_BASE + offset), value);
-}
-
-/* pm read/write - access registers at 0xfed80300 */
-
-u8 pm_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_PMIO_BASE + reg));
-}
-
-u16 pm_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_PMIO_BASE + reg));
-}
-
-u32 pm_read32(u8 reg)
-{
- return read32((void *)(ACPIMMIO_PMIO_BASE + reg));
-}
-
-void pm_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_PMIO_BASE + reg), value);
-}
-
-void pm_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_PMIO_BASE + reg), value);
-}
-
-void pm_write32(u8 reg, u32 value)
-{
- write32((void *)(ACPIMMIO_PMIO_BASE + reg), value);
-}
-
-/* pm2 read/write - access registers at 0xfed80400 - currently unused */
-
-/* biosram read/write - access registers at 0xfed80500 */
-
-uint8_t biosram_read8(uint8_t offset)
-{
- return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset));
-}
-
-uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */
-{
- int i;
- uint16_t value = 0;
- for (i = sizeof(value) - 1 ; i >= 0 ; i--)
- value = (value << 8) | biosram_read8(offset + i);
- return value;
-}
-
-uint32_t biosram_read32(uint8_t offset)
-{
- uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16;
- return value | biosram_read16(offset);
-}
-
-void biosram_write8(uint8_t offset, uint8_t value)
-{
- write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value);
-}
-
-void biosram_write16(uint8_t offset, uint16_t value)
-{
- int i;
- for (i = 0 ; i < sizeof(value) ; i++) {
- biosram_write8(offset + i, value & 0xff);
- value >>= 8;
- }
-}
-
-void biosram_write32(uint8_t offset, uint32_t value)
-{
- int i;
- for (i = 0 ; i < sizeof(value) ; i++) {
- biosram_write8(offset + i, value & 0xff);
- value >>= 8;
- }
-}
-
-/* cmosram read/write - access registers at 0xfed80600 - currently unused */
-
-/* cmos read/write - access registers at 0xfed80700 - currently unused */
-
-/* acpi read/write - access registers at 0xfed80800 */
-
-u8 acpi_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_ACPI_BASE + reg));
-}
-
-u16 acpi_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_ACPI_BASE + reg));
-}
-
-u32 acpi_read32(u8 reg)
-{
- return read32((void *)(ACPIMMIO_ACPI_BASE + reg));
-}
-
-void acpi_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_ACPI_BASE + reg), value);
-}
-
-void acpi_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_ACPI_BASE + reg), value);
-}
-
-void acpi_write32(u8 reg, u32 value)
-{
- write32((void *)(ACPIMMIO_ACPI_BASE + reg), value);
-}
-
-/* asf read/write - access registers at 0xfed80900 - not currently used */
-
-u8 asf_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_ASF_BASE + reg));
-}
-
-u16 asf_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_ASF_BASE + reg));
-}
-
-void asf_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_ASF_BASE + reg), value);
-}
-
-void asf_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_ASF_BASE + reg), value);
-}
-
-/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */
-
-u8 smbus_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_SMBUS_BASE + reg));
-}
-
-u16 smbus_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_SMBUS_BASE + reg));
-}
-
-void smbus_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
-}
-
-void smbus_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value);
-}
-
-/* wdt read/write - access registers at 0xfed80b00 - not currently used */
-
-/* hpet read/write - access registers at 0xfed80c00 - not currently used */
-
-/* iomux read/write - access registers at 0xfed80d00 */
-
-u8 iomux_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_IOMUX_BASE + reg));
-}
-
-u16 iomux_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_IOMUX_BASE + reg));
-}
-
-u32 iomux_read32(u8 reg)
-{
- return read32((void *)(ACPIMMIO_IOMUX_BASE + reg));
-}
-
-void iomux_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
-}
-
-void iomux_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
-}
-
-void iomux_write32(u8 reg, u32 value)
-{
- write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value);
-}
-
-/* misc read/write - access registers at 0xfed80e00 */
-
-u8 misc_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_MISC_BASE + reg));
-}
-
-u16 misc_read16(u8 reg)
-{
- return read16((void *)(ACPIMMIO_MISC_BASE + reg));
-}
-
-u32 misc_read32(u8 reg)
-{
- return read32((void *)(ACPIMMIO_MISC_BASE + reg));
-}
-
-void misc_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_MISC_BASE + reg), value);
-}
-
-void misc_write16(u8 reg, u16 value)
-{
- write16((void *)(ACPIMMIO_MISC_BASE + reg), value);
-}
-
-void misc_write32(u8 reg, u32 value)
-{
- write32((void *)(ACPIMMIO_MISC_BASE + reg), value);
-}
-
-/* dpvga read/write - access registers at 0xfed81400 - not currently used */
-
-/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */
-/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */
-/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */
-
-/* xhci_pm read/write - access registers at 0xfed81c00 */
-
-uint8_t xhci_pm_read8(uint8_t reg)
-{
- return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg));
-}
-
-uint16_t xhci_pm_read16(uint8_t reg)
-{
- return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg));
-}
-
-uint32_t xhci_pm_read32(uint8_t reg)
-{
- return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg));
-}
-
-void xhci_pm_write8(uint8_t reg, uint8_t value)
-{
- write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
-}
-
-void xhci_pm_write16(uint8_t reg, uint16_t value)
-{
- write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
-}
-
-void xhci_pm_write32(uint8_t reg, uint32_t value)
-{
- write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value);
-}
-
-/* acdc_tmr read/write - access registers at 0xfed81d00 */
-
-/* aoac read/write - access registers at 0xfed81e00 - not currently used */
-
-u8 aoac_read8(u8 reg)
-{
- return read8((void *)(ACPIMMIO_AOAC_BASE + reg));
-}
-
-void aoac_write8(u8 reg, u8 value)
-{
- write8((void *)(ACPIMMIO_AOAC_BASE + reg), value);
-}
-
uint16_t pm_acpi_pm_cnt_blk(void)
{
return pm_read16(PM1_CNT_BLK);
diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c
index 6285d793b7..df7a86edc7 100644
--- a/src/soc/amd/stoneyridge/smbus.c
+++ b/src/soc/amd/stoneyridge/smbus.c
@@ -16,6 +16,7 @@
#include <arch/io.h>
#include <stdint.h>
#include <console/console.h>
+#include <amdblocks/acpimmio.h>
#include <soc/smbus.h>
#include <soc/southbridge.h>
diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
index 5ddc0dda62..4a0d833c7b 100644
--- a/src/soc/amd/stoneyridge/smi.c
+++ b/src/soc/amd/stoneyridge/smi.c
@@ -19,6 +19,7 @@
*/
#include <console/console.h>
+#include <amdblocks/acpimmio.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c
index 91b86e284e..8759e2acb1 100644
--- a/src/soc/amd/stoneyridge/smi_util.c
+++ b/src/soc/amd/stoneyridge/smi_util.c
@@ -21,6 +21,7 @@
#include <console/console.h>
#include <soc/southbridge.h>
#include <soc/smi.h>
+#include <amdblocks/acpimmio.h>
void configure_smi(uint8_t smi_num, uint8_t mode)
{
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c
index c3f4b675dc..c3aed578ff 100644
--- a/src/soc/amd/stoneyridge/smihandler.c
+++ b/src/soc/amd/stoneyridge/smihandler.c
@@ -24,6 +24,7 @@
#include <device/pci_def.h>
#include <soc/smi.h>
#include <soc/southbridge.h>
+#include <amdblocks/acpimmio.h>
#include <elog.h>
/* bits in smm_io_trap */
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index b6c40b63d3..bf8787c1fc 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -27,6 +27,7 @@
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/reset.h>
+#include <amdblocks/acpimmio.h>
#include <soc/southbridge.h>
#include <soc/smbus.h>
#include <soc/smi.h>
@@ -359,16 +360,6 @@ void sb_lpc_decode(void)
pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp);
}
-void sb_acpi_mmio_decode(void)
-{
- uint8_t byte;
-
- /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */
- byte = pm_io_read8(PM_ISA_CONTROL);
- byte |= MMIO_EN;
- pm_io_write8(PM_ISA_CONTROL, byte);
-}
-
static void sb_enable_cf9_io(void)
{
uint32_t reg = pm_read32(PM_DECODE_EN);
@@ -642,7 +633,7 @@ void bootblock_fch_early_init(void)
sb_lpc_early_setup();
sb_spibase();
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
- sb_acpi_mmio_decode();
+ enable_acpimmio_decode();
fch_smbus_init();
sb_enable_cf9_io();
setup_spread_spectrum(&reboot);
diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c
index f2fa3ba267..00f82375e8 100644
--- a/src/soc/amd/stoneyridge/usb.c
+++ b/src/soc/amd/stoneyridge/usb.c
@@ -22,7 +22,7 @@
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
-
+#include <amdblocks/acpimmio.h>
static void set_usb_over_current(struct device *dev)
{