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-rw-r--r--src/southbridge/amd/rs780/cmn.c2
-rw-r--r--src/southbridge/amd/sr5650/sr5650.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 3c6d22dda5..cf09b9a89d 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -301,7 +301,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
/* 4 means 7:4 and 15:12
* 3 means 7:2 and 15:10
* 2 means 7:1 and 15:9
- * egnoring the reversal case
+ * ignoring the reversal case
*/
lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel);
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 0bb246e9ed..7fdecf1dae 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -202,7 +202,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
/* 4 means 7:4 and 15:12
* 3 means 7:2 and 15:10
* 2 means 7:1 and 15:9
- * egnoring the reversal case
+ * ignoring the reversal case
*/
lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel);