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-rw-r--r--Documentation/releases/coreboot-4.8.1-relnotes.md2
-rw-r--r--Documentation/soc/intel/fit.md2
-rw-r--r--Documentation/tutorial/part1.md2
-rw-r--r--payloads/external/SeaBIOS/Kconfig2
-rw-r--r--src/cpu/x86/smm/smm_module_loader.c2
-rw-r--r--src/device/Kconfig2
-rw-r--r--src/device/oprom/include/x86emu/x86emu.h2
-rw-r--r--src/drivers/intel/gma/int15.c2
-rw-r--r--src/mainboard/asus/p8z77-m_pro/cmos.layout2
-rw-r--r--src/mainboard/asus/p8z77-m_pro/early_init.c2
-rw-r--r--src/mainboard/google/cyan/Kconfig4
-rw-r--r--src/mainboard/google/link/mainboard.c6
-rw-r--r--src/mainboard/google/rambi/mainboard.c2
-rw-r--r--src/mainboard/intel/strago/Kconfig4
-rw-r--r--src/mainboard/kontron/ktqm77/mainboard.c6
-rw-r--r--src/mainboard/lenovo/t420/early_init.c2
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/common/block/fast_spi/fast_spi.c2
-rw-r--r--src/soc/intel/common/pch/lockdown/lockdown.c6
-rw-r--r--src/soc/intel/skylake/lockdown.c2
-rw-r--r--util/inteltool/inteltool.82
-rw-r--r--util/inteltool/spi.c2
22 files changed, 30 insertions, 30 deletions
diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md
index 8a6ab964e8..e2462365ac 100644
--- a/Documentation/releases/coreboot-4.8.1-relnotes.md
+++ b/Documentation/releases/coreboot-4.8.1-relnotes.md
@@ -40,7 +40,7 @@ possible
Lenovo mainboards
-----------------
-* Started integration of VBT (Video Bios Table) binary files to
+* Started integration of VBT (Video BIOS Table) binary files to
support native graphics initialisation
Internal changes
diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md
index 8b638f0433..553fef3c16 100644
--- a/Documentation/soc/intel/fit.md
+++ b/Documentation/soc/intel/fit.md
@@ -57,4 +57,4 @@ execution of the IA32 reset vector happens.
## References
* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf)
-* [FIT bios specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf)
+* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf)
diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md
index 0c7ef67cbb..7e3da01572 100644
--- a/Documentation/tutorial/part1.md
+++ b/Documentation/tutorial/part1.md
@@ -173,7 +173,7 @@ Here's the command line instruction broken down:
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to
ISA bridge.
* `-bios build/coreboot.rom`
-Use the bios rom image that we just built. If this flag is left out, the
+Use the coreboot rom image that we just built. If this flag is left out, the
standard SeaBIOS image that comes with QEMU is used.
* `-serial stdio`
Send the serial output to the console. This allows you to view the coreboot
diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
index 8ec7361813..e816775f28 100644
--- a/payloads/external/SeaBIOS/Kconfig
+++ b/payloads/external/SeaBIOS/Kconfig
@@ -125,7 +125,7 @@ config SEABIOS_DEBUG_LEVEL
level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM
level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h
level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts
- level 4 - bios tables, more optionrom
+ level 4 - BIOS tables, more optionrom
level 5 - Extra bootsplash, more XHCI
level 6 - ATA commands, extra optionrom
level 7 - extra ps2 commands, more OHCI & EHCI
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index 66a40c4233..ca6f611959 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -396,7 +396,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
/* Does the required amount of memory exceed the SMRAM region size? */
total_size = total_stack_size + handler_size;
total_size += fxsave_size + SMM_DEFAULT_SIZE;
- // account for the bios resource list
+ // account for the BIOS resource list
if (CONFIG(STM))
total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE;
diff --git a/src/device/Kconfig b/src/device/Kconfig
index a25bb911c9..603c7eb8d1 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -721,7 +721,7 @@ config INTEL_GMA_HAVE_VBT
config INTEL_GMA_ADD_VBT
depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON
- bool "Add a Video Bios Table (VBT) binary to CBFS"
+ bool "Add a Video BIOS Table (VBT) binary to CBFS"
default y if INTEL_GMA_HAVE_VBT
help
Add a VBT data file to CBFS. The VBT describes the integrated
diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h
index 4ae82d96ff..e7f48e4ade 100644
--- a/src/device/oprom/include/x86emu/x86emu.h
+++ b/src/device/oprom/include/x86emu/x86emu.h
@@ -170,7 +170,7 @@ void X86EMU_halt_sys(void);
#define DEBUG_SVC_F 0x000020
#define DEBUG_FS_F 0x000080
#define DEBUG_PROC_F 0x000100
-#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */
+#define DEBUG_SYSINT_F 0x000200 /* BIOS system interrupts. */
#define DEBUG_TRACECALL_F 0x000400
#define DEBUG_INSTRUMENT_F 0x000800
#define DEBUG_MEM_TRACE_F 0x001000
diff --git a/src/drivers/intel/gma/int15.c b/src/drivers/intel/gma/int15.c
index 7e0ece3382..11efe8c57d 100644
--- a/src/drivers/intel/gma/int15.c
+++ b/src/drivers/intel/gma/int15.c
@@ -33,7 +33,7 @@ int intel_vga_int15_handler(void)
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
+ * 0 = video BIOS default
*/
X86_AX = 0x005f;
X86_CX = pfit;
diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout
index da29d1c10e..4ac7b5d2eb 100644
--- a/src/mainboard/asus/p8z77-m_pro/cmos.layout
+++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout
@@ -77,7 +77,7 @@ entries
421 2 e 8 usb3_mode
# usb3_drv
-# Load (or not) pre-OS xHCI USB3 bios driver
+# Load (or not) pre-OS xHCI USB3 BIOS driver
#
423 1 e 1 usb3_drv
diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c
index 800d975d0f..6c76a7ac29 100644
--- a/src/mainboard/asus/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8z77-m_pro/early_init.c
@@ -115,7 +115,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* SMBus mul 2 */
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
- .ec_present = 0, /* Asus 2203 bios shows XUECA016, but no EC */
+ .ec_present = 0, /* Asus 2203 BIOS shows XUECA016, but no EC */
.gbe_enable = 0, /* Board uses no Intel GbE but a RTL8111F */
.dimm_channel0_disabled = 0, /* Both DIMM enabled */
.dimm_channel1_disabled = 0, /* Both DIMM enabled */
diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig
index 6331419cd3..94ffbc0bad 100644
--- a/src/mainboard/google/cyan/Kconfig
+++ b/src/mainboard/google/cyan/Kconfig
@@ -78,7 +78,7 @@ config VGA_BIOS_FILE
depends on VGA_BIOS
default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"
help
- The C0 version of the video bios gets computed from this name
+ The C0 version of the video BIOS gets computed from this name
so that they can both be added. Only the correct one for the
system will be run.
@@ -87,7 +87,7 @@ config VGA_BIOS_ID
depends on VGA_BIOS
default "8086,22b0"
help
- The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
+ The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1
config CBFS_SIZE
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 8be4012263..32e5487278 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -47,10 +47,10 @@ static int int15_handler(void)
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
+ * 0 = video BIOS default
*/
X86_AX = 0x005f;
- X86_CL = 0x00; /* Use video bios default */
+ X86_CL = 0x00; /* Use video BIOS default */
res = 1;
break;
case 0x5f35:
@@ -66,7 +66,7 @@ static int int15_handler(void)
* bit 7 = LFP2
*/
X86_AX = 0x005f;
- X86_CX = 0x0000; /* Use video bios default */
+ X86_CX = 0x0000; /* Use video BIOS default */
res = 1;
break;
case 0x5f51:
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index d4e38d0532..7e9b343880 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -48,7 +48,7 @@ static int int15_handler(void)
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
+ * 0 = video BIOS default
*/
X86_AX = 0x005f;
X86_CX = 0x0001;
diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig
index 5e710a52bf..640f5d4e91 100644
--- a/src/mainboard/intel/strago/Kconfig
+++ b/src/mainboard/intel/strago/Kconfig
@@ -35,7 +35,7 @@ config VGA_BIOS_FILE
depends on VGA_BIOS
default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"
help
- The C0 version of the video bios gets computed from this name
+ The C0 version of the video BIOS gets computed from this name
so that they can both be added. Only the correct one for the
system will be run.
@@ -44,7 +44,7 @@ config VGA_BIOS_ID
depends on VGA_BIOS
default "8086,22b0"
help
- The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
+ The VGA_BIOS_ID for the C0 version of the video BIOS is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1
config EC_GOOGLE_CHROMEEC_BOARDNAME
diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c
index 2af5eb239f..5cd3fc4234 100644
--- a/src/mainboard/kontron/ktqm77/mainboard.c
+++ b/src/mainboard/kontron/ktqm77/mainboard.c
@@ -41,12 +41,12 @@ static int int15_handler(void)
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
- * 0 = video bios default
+ * 0 = video BIOS default
*/
X86_EAX &= 0xffff0000;
X86_EAX |= 0x005f;
X86_ECX &= 0xffffff00;
- X86_ECX |= 0x00; /* Use video bios default */
+ X86_ECX |= 0x00; /* Use video BIOS default */
res = 1;
break;
case 0x5f35:
@@ -64,7 +64,7 @@ static int int15_handler(void)
X86_EAX &= 0xffff0000;
X86_EAX |= 0x005f;
X86_ECX &= 0xffff0000;
- X86_ECX |= 0x0000; /* Use video bios default */
+ X86_ECX |= 0x0000; /* Use video BIOS default */
res = 1;
break;
case 0x5f51:
diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c
index 2e39885b6b..c675512d6f 100644
--- a/src/mainboard/lenovo/t420/early_init.c
+++ b/src/mainboard/lenovo/t420/early_init.c
@@ -48,7 +48,7 @@ static void hybrid_graphics_init(void)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
-// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
+// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* P0: system port 4, OC0 */
{ 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index d9c42f9c20..b9c5a4fa27 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -733,7 +733,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Enable Audio clk gate and power gate */
silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
- /* Bios config lockdown Audio clk and power gate */
+ /* BIOS config lockdown Audio clk and power gate */
silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
if (CONFIG(SOC_INTEL_GLK))
glk_fsp_silicon_init_params_cb(cfg, silconfig);
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 019976ad8c..49284e9489 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -237,7 +237,7 @@ void fast_spi_cache_bios_region(void)
/* LOCAL APIC default address is 0xFEE0000, bios_size over 16MB will
* cause memory type conflict when setting memory type to write
- * protection, so limit the cached bios region to be no more than 16MB.
+ * protection, so limit the cached BIOS region to be no more than 16MB.
* */
bios_size = MIN(bios_size, 16 * MiB);
if (bios_size <= 0)
diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c
index 4a3209e03e..3fa6e77042 100644
--- a/src/soc/intel/common/pch/lockdown/lockdown.c
+++ b/src/soc/intel/common/pch/lockdown/lockdown.c
@@ -69,12 +69,12 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
/* Lock FAST_SPIBAR */
fast_spi_lock_bar();
- /* Set Bios Interface Lock, Bios Lock */
+ /* Set BIOS Interface Lock, BIOS Lock */
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
- /* Bios Interface Lock */
+ /* BIOS Interface Lock */
fast_spi_set_bios_interface_lock_down();
- /* Bios Lock */
+ /* BIOS Lock */
fast_spi_set_lock_enable();
}
}
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
index 66dae8c73c..6911744bcb 100644
--- a/src/soc/intel/skylake/lockdown.c
+++ b/src/soc/intel/skylake/lockdown.c
@@ -22,7 +22,7 @@
static void lpc_lockdown_config(int chipset_lockdown)
{
- /* Set Bios Interface Lock, Bios Lock */
+ /* Set BIOS Interface Lock, BIOS Lock */
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
lpc_set_bios_interface_lock_down();
lpc_set_lock_enable();
diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8
index 86a76bdc9a..01e3cfd7f2 100644
--- a/util/inteltool/inteltool.8
+++ b/util/inteltool/inteltool.8
@@ -32,7 +32,7 @@ Show only GPIO register differences from hardware defaults.
Dump I/O Controller Hub (ICH) southbridge RCBA registers.
.TP
.B "\-s, \-\-spi"
-Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control.
+Dump I/O Controller Hub (ICH) southbridge SPI registers and BIOS control.
.TP
.B "\-f, \-\-gfx"
.RB "Dump graphics registers. " \
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index 22ba3d42f2..e8289acaf3 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -22,7 +22,7 @@ static const io_register_t pch_bios_cntl_registers[] = {
{ 0x1, 1, "BLE - lock enable" },
{ 0x2, 2, "SPI Read configuration" },
{ 0x4, 1, "TopSwapStatus" },
- { 0x5, 1, "SMM Bios Write Protect Disable" },
+ { 0x5, 1, "SMM BIOS Write Protect Disable" },
{ 0x6, 2, "reserved" },
};