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-rw-r--r--src/southbridge/amd/sr5650/pcie.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 762e632c2a..e198b87324 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -768,11 +768,12 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
if (res) {
AtiPcieCfg.PortDetect |= 1 << port;
} else {
- /* If the training failed the disable the bridge to prevent subsequent
- * lockup on bridge configuration register read during the PCI bus scan
+ /* Even though nothing is attached to this port
+ * the port needs to be "enabled" to obtain
+ * a bus number from the PCI resource allocator
*/
training_ok = 0;
- dev->enabled = 0;
+ dev->enabled = 1;
}
}
}