diff options
| -rw-r--r-- | payloads/libpayload/include/coreboot_tables.h | 2 | ||||
| -rw-r--r-- | payloads/libpayload/include/sysinfo.h | 4 | ||||
| -rw-r--r-- | payloads/libpayload/libc/coreboot.c | 12 | ||||
| -rw-r--r-- | src/arch/x86/smbios.c | 2 | ||||
| -rw-r--r-- | src/commonlib/include/commonlib/coreboot_tables.h | 2 | ||||
| -rw-r--r-- | src/lib/coreboot_table.c | 17 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/gnvs.c | 32 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/gnvs.h | 9 |
8 files changed, 44 insertions, 36 deletions
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 6b6d1b421e..4cf57c53a3 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -200,7 +200,7 @@ struct cb_gpios { struct cb_gpio gpios[0]; }; -#define CB_TAG_VDAT 0x0015 +#define CB_TAG_CHROMEOS_ACPI 0x0015 #define CB_TAG_VBNV 0x0019 #define CB_TAG_VBOOT_HANDOFF 0x0020 #define CB_TAG_DMA 0x0022 diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index f221a15faa..66933e3da0 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -97,8 +97,8 @@ struct sysinfo_t { void *vboot_handoff; u32 vboot_handoff_size; - void *vdat_addr; - u32 vdat_size; + void *chromeos_acpi_addr; + u32 chromeos_acpi_size; #if IS_ENABLED(CONFIG_LP_ARCH_X86) int x86_rom_var_mtrr_index; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index d831b96ba2..b8799871d5 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -106,12 +106,12 @@ static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info) info->gpios[i] = gpios->gpios[i]; } -static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info) +static void cb_parse_chromeos_acpi(unsigned char *ptr, struct sysinfo_t *info) { - struct lb_range *vdat = (struct lb_range *) ptr; + struct lb_range *chromeos_acpi = (struct lb_range *) ptr; - info->vdat_addr = phys_to_virt(vdat->range_start); - info->vdat_size = vdat->range_size; + info->chromeos_acpi_addr = phys_to_virt(chromeos_acpi->range_start); + info->chromeos_acpi_size = chromeos_acpi->range_size; } static void cb_parse_mac_addresses(unsigned char *ptr, @@ -357,8 +357,8 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_GPIO: cb_parse_gpios(ptr, info); break; - case CB_TAG_VDAT: - cb_parse_vdat(ptr, info); + case CB_TAG_CHROMEOS_ACPI: + cb_parse_chromeos_acpi(ptr, info); break; case CB_TAG_VBNV: cb_parse_vbnv(ptr, info); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 582ae8da11..103b4aef7e 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -367,7 +367,7 @@ static int smbios_write_type0(unsigned long *current, int handle) #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) /* SMBIOS offsets start at 1 rather than 0 */ - vboot_data->vbt10 = (u32)t->eos + (version_offset - 1); + acpi_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1); #endif #endif /* CONFIG_CHROMEOS */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 806dfc76d4..34726abab3 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -290,7 +290,7 @@ struct lb_gpios { struct lb_gpio gpios[0]; }; -#define LB_TAG_VDAT 0x0015 +#define LB_TAG_CHROMEOS_ACPI 0x0015 #define LB_TAG_VBNV 0x0019 #define LB_TAB_VBOOT_HANDOFF 0x0020 #define LB_TAB_DMA 0x0022 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 2d74c8ec7f..6b0e1a0237 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -195,15 +195,16 @@ static void lb_gpios(struct lb_header *header) } } -static void lb_vdat(struct lb_header *header) +static void lb_chromeos_acpi(struct lb_header *header) { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - struct lb_range *vdat; + struct lb_range *chromeos_acpi; - vdat = (struct lb_range *)lb_new_record(header); - vdat->tag = LB_TAG_VDAT; - vdat->size = sizeof(*vdat); - acpi_get_vdat_info(&vdat->range_start, &vdat->range_size); + chromeos_acpi = (struct lb_range *)lb_new_record(header); + chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI; + chromeos_acpi->size = sizeof(*chromeos_acpi); + acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start, + &chromeos_acpi->range_size); #endif } @@ -546,8 +547,8 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) /* Record our GPIO settings (ChromeOS specific) */ lb_gpios(head); - /* pass along the VDAT buffer address */ - lb_vdat(head); + /* pass along the chromeos_acpi_t buffer address */ + lb_chromeos_acpi(head); /* pass along VBNV offsets in CMOS */ lb_vbnv(head); diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index a278b4109c..70aa899042 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -27,40 +27,46 @@ #include "chromeos.h" #include "gnvs.h" -chromeos_acpi_t *vboot_data = NULL; +static chromeos_acpi_t *chromeos_acpi; static u32 me_hash_saved[8]; -void chromeos_init_vboot(chromeos_acpi_t *chromeos) +void chromeos_init_vboot(chromeos_acpi_t *init) { - vboot_data = chromeos; + chromeos_acpi = init; /* Copy saved ME hash into NVS */ - memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh)); + memcpy(chromeos_acpi->mehh, me_hash_saved, sizeof(chromeos_acpi->mehh)); struct vboot_handoff *vboot_handoff; if (vboot_get_handoff_info((void **)&vboot_handoff, NULL) == 0) - memcpy(&chromeos->vdat[0], &vboot_handoff->shared_data[0], - ARRAY_SIZE(chromeos->vdat)); + memcpy(&chromeos_acpi->vdat[0], &vboot_handoff->shared_data[0], + ARRAY_SIZE(chromeos_acpi->vdat)); - chromeos_ram_oops_init(chromeos); + chromeos_ram_oops_init(chromeos_acpi); } void chromeos_set_me_hash(u32 *hash, int len) { - if ((len*sizeof(u32)) > sizeof(vboot_data->mehh)) + if ((len*sizeof(u32)) > sizeof(chromeos_acpi->mehh)) return; /* Copy to NVS or save until it is ready */ - if (vboot_data) + if (chromeos_acpi) /* This does never happen! */ - memcpy(vboot_data->mehh, hash, len*sizeof(u32)); + memcpy(chromeos_acpi->mehh, hash, len*sizeof(u32)); else memcpy(me_hash_saved, hash, len*sizeof(u32)); } -void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size) +void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr, + uint32_t *chromeos_acpi_size) { - *vdat_addr = (intptr_t)vboot_data; - *vdat_size = sizeof(*vboot_data); + *chromeos_acpi_addr = (intptr_t)chromeos_acpi; + *chromeos_acpi_size = sizeof(*chromeos_acpi); +} + +chromeos_acpi_t *acpi_get_chromeos_acpi(void) +{ + return chromeos_acpi; } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 82cd409e8e..e865c0e832 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -53,7 +53,7 @@ typedef struct { u32 vbt7; // 18e active main firmware type u32 vbt8; // 192 recovery reason u32 vbt9; // 196 fmap base address - u8 vdat[3072]; // 19a + u8 vdat[3072]; // 19a VDAT space filled by verified boot u32 vbt10; // d9a smbios bios version u32 mehh[8]; // d9e management engine hash u32 ramoops_base; // dbe ramoops base address @@ -61,9 +61,10 @@ typedef struct { u8 pad[314]; // dc6-eff } __packed chromeos_acpi_t; -extern chromeos_acpi_t *vboot_data; -void chromeos_init_vboot(chromeos_acpi_t *chromeos); +void chromeos_init_vboot(chromeos_acpi_t *init); void chromeos_set_me_hash(u32*, int); -void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size); +void acpi_get_chromeos_acpi_info(uint64_t *chromeos_acpi_addr, + uint32_t *chromeos_acpi_size); +chromeos_acpi_t *acpi_get_chromeos_acpi(void); #endif |