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-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 47abadc5d9..0b8e5c6519 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -33,6 +33,11 @@ chip soc/intel/cannonlake
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "SlowSlewRateForFivr" = "2"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port