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-rw-r--r--src/mainboard/lenovo/x201/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/x201/gpio.c (renamed from src/mainboard/lenovo/x201/gpio.h)2
-rw-r--r--src/mainboard/lenovo/x201/romstage.c4
3 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc
index 46f98fa5fc..e91fd6babd 100644
--- a/src/mainboard/lenovo/x201/Makefile.inc
+++ b/src/mainboard/lenovo/x201/Makefile.inc
@@ -17,3 +17,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += dock.c
ramstage-y += dock.c
+romstage-y += gpio.c \ No newline at end of file
diff --git a/src/mainboard/lenovo/x201/gpio.h b/src/mainboard/lenovo/x201/gpio.c
index fe3e9f5193..95b017c170 100644
--- a/src/mainboard/lenovo/x201/gpio.h
+++ b/src/mainboard/lenovo/x201/gpio.c
@@ -378,7 +378,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio75 = GPIO_LEVEL_LOW,
};
-const struct pch_gpio_map x201_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 107cc46fc8..7634de8e98 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -37,10 +37,10 @@
#include <cbmem.h>
#include <tpm.h>
-#include "gpio.h"
#include "dock.h"
#include "arch/early_variables.h"
#include <southbridge/intel/ibexpeak/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <northbridge/intel/nehalem/nehalem.h>
#include <northbridge/intel/nehalem/raminit.h>
@@ -200,7 +200,7 @@ void mainboard_romstage_entry(unsigned long bist)
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
- setup_pch_gpios(&x201_gpio_map);
+ setup_pch_gpios(&mainboard_gpio_map);
/* This should probably go away. Until now it is required