diff options
| -rw-r--r-- | src/soc/amd/stoneyridge/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/early_setup.c | 33 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/hudson.c | 21 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/pci_devs.h | 6 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/pci.c | 67 |
5 files changed, 21 insertions, 107 deletions
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 7ced68887b..bc128a13d1 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -59,7 +59,6 @@ ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c ramstage-y += model_15_init.c ramstage-y += northbridge.c -ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += reset.c ramstage-y += sata.c diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index 3c58e38540..68bccc4456 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -55,39 +55,6 @@ void hudson_pci_port80(void) u8 byte; pci_devfn_t dev; - /* P2P Bridge */ - dev = PCI_DEV(0, SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC); - - /* Chip Control: Enable subtractive decoding */ - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 5; - pci_write_config8(dev, 0x40, byte); - - /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ - byte = pci_read_config8(dev, 0x4b); - byte |= 1 << 7; - pci_write_config8(dev, 0x4b, byte); - - /* The same IO Base and IO Limit here is meaningful because we set the - * bridge to be subtractive. During early setup stage, we have to make - * sure that data can go through port 0x80. - */ - /* IO Base: 0xf000 */ - byte = pci_read_config8(dev, 0x1c); - byte |= 0xf << 4; - pci_write_config8(dev, 0x1c, byte); - - /* IO Limit: 0xf000 */ - byte = pci_read_config8(dev, 0x1d); - byte |= 0xf << 4; - pci_write_config8(dev, 0x1d, byte); - - /* PCI Command: Enable IO response */ - byte = pci_read_config8(dev, 0x04); - byte |= 1 << 0; - pci_write_config8(dev, 0x04, byte); - - /* LPC controller */ dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); byte = pci_read_config8(dev, 0x4a); diff --git a/src/soc/amd/stoneyridge/hudson.c b/src/soc/amd/stoneyridge/hudson.c index e75a8091ee..af1095c819 100644 --- a/src/soc/amd/stoneyridge/hudson.c +++ b/src/soc/amd/stoneyridge/hudson.c @@ -17,12 +17,14 @@ #include <arch/io.h> #include <arch/acpi.h> +#include <bootstate.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <amd_pci_util.h> #include <soc/hudson.h> #include <soc/smbus.h> #include <soc/smi.h> @@ -130,3 +132,22 @@ void hudson_final(void *chip_info) #endif #endif } + +/* + * Update the PCI devices with a valid IRQ number + * that is set in the mainboard PCI_IRQ structures. + */ +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index f0445422a9..33973e2f53 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -90,12 +90,6 @@ #define LPC_DEVID 0x780e #define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) -/* PCI Ports */ -#define SB_PCI_PORT_DEV 0x14 -#define SB_PCI_PORT_FUNC 4 -#define SB_PCI_PORT_DEVID 0x780f -#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) - /* SD Controller */ #define SD_DEV 0x14 #define SD_FUNC 7 diff --git a/src/soc/amd/stoneyridge/pci.c b/src/soc/amd/stoneyridge/pci.c deleted file mode 100644 index 61d7a39a97..0000000000 --- a/src/soc/amd/stoneyridge/pci.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <soc/hudson.h> -#include <amd_pci_util.h> -#include <bootstate.h> - -static void pci_init(struct device *dev) -{ -} - -/* - * Update the PCI devices with a valid IRQ number - * that is set in the mainboard PCI_IRQ structures. - */ -static void set_pci_irqs(void *unused) -{ - /* Write PCI_INTR regs 0xC00/0xC01 */ - write_pci_int_table(); - - /* Write IRQs for all devicetree enabled devices */ - write_pci_cfg_irqs(); -} - -/* - * Hook this function into the PCI state machine - * on entry into BS_DEV_ENABLE. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_SB900_PCI, -}; |