summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c34
-rw-r--r--src/soc/intel/tigerlake/espi.c8
-rw-r--r--src/soc/intel/tigerlake/include/soc/pch.h4
3 files changed, 31 insertions, 15 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 1ef4928fa6..8599423f91 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -37,7 +37,8 @@
#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP 0x0600
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP 0x0980
#define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4
#define PCR_PSFX_TO_SHDW_BAR2 0x8
@@ -57,6 +58,20 @@
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
+static uint32_t get_pmc_reg_base(void)
+{
+ uint8_t pch_series;
+
+ pch_series = get_pch_series();
+
+ if (pch_series == PCH_TGP)
+ return PCR_PSF3_TO_SHDW_PMC_REG_BASE_TGP;
+ else if (pch_series == PCH_JSP)
+ return PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP;
+ else
+ return 0;
+}
+
static void soc_config_pwrmbase(void)
{
uint32_t reg32;
@@ -99,22 +114,23 @@ void bootblock_pch_early_init(void)
static void soc_config_acpibase(void)
{
uint32_t pmc_reg_value;
+ uint32_t pmc_base_reg;
+
+ pmc_base_reg = get_pmc_reg_base();
+ if (!pmc_base_reg)
+ die_with_post_code(POST_HW_INIT_FAILURE, "Invalid PMC base address\n");
- pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
- PCR_PSFX_TO_SHDW_BAR4);
+ pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
if (pmc_reg_value != 0xffffffff) {
/* Disable Io Space before changing the address */
- pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
- PCR_PSFX_T0_SHDW_PCIEN,
+ pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
/* Program ABASE in PSF3 PMC space BAR4*/
- pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
- PCR_PSFX_TO_SHDW_BAR4,
+ pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
ACPI_BASE_ADDRESS);
/* Enable IO Space */
- pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
- PCR_PSFX_T0_SHDW_PCIEN,
+ pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
}
}
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
index 932f76089d..d07a582a32 100644
--- a/src/soc/intel/tigerlake/espi.c
+++ b/src/soc/intel/tigerlake/espi.c
@@ -81,10 +81,10 @@ uint8_t get_pch_series(void)
*/
lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1);
- if (lpc_did_hi_byte == 0x9D)
- return PCH_LP;
- else if (lpc_did_hi_byte == 0xA3)
- return PCH_H;
+ if (lpc_did_hi_byte == 0xA0)
+ return PCH_TGP;
+ else if (lpc_did_hi_byte == 0x38)
+ return PCH_JSP;
else
return PCH_UNKNOWN_SERIES;
}
diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h
index 57ddeaf97f..ae8e310afb 100644
--- a/src/soc/intel/tigerlake/include/soc/pch.h
+++ b/src/soc/intel/tigerlake/include/soc/pch.h
@@ -18,8 +18,8 @@
#include <stdint.h>
-#define PCH_H 1
-#define PCH_LP 2
+#define PCH_TGP 1
+#define PCH_JSP 2
#define PCH_UNKNOWN_SERIES 0xFF
#define PCIE_CLK_NOTUSED 0xFF