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-rw-r--r--src/soc/amd/stoneyridge/gpio.c10
-rw-r--r--src/soc/amd/stoneyridge/include/soc/gpio.h1
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index 1b7f0557df..3bb77b7010 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <gpio.h>
#include <soc/gpio.h>
+#include <soc/southbridge.h>
#include <assert.h>
#include <compiler.h>
@@ -97,6 +98,11 @@ static void program_smi(uint32_t flag, int gevent_num)
SMI_SCI_LVL_LOW);
}
+static void route_sci(uint8_t event)
+{
+ smi_write8(SMI_SCI_MAP(event), event);
+}
+
static void get_sci_config_bits(uint32_t flag, uint32_t *edge, uint32_t *level)
{
uint32_t trigger;
@@ -232,6 +238,9 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
write8(mux_ptr, mux & AMD_GPIO_MUX_MASK);
+ /* special case if pin 2 is assigned to wake */
+ if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK))
+ route_sci(GPIO_2_EVENT);
gpio_ptr = (uint32_t *)gpio_get_address(gpio);
if (control_flags & GPIO_SPECIAL_FLAG) {
@@ -267,6 +276,7 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
edge_level |= bit_edge << gevent_num;
direction |= bit_level << gevent_num;
mask |= (1 << gevent_num);
+ route_sci(gevent_num);
break;
default:
printk(BIOS_WARNING, "Error, flags 0x%08x\n",
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index e43f2c7306..6133bf1684 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -368,6 +368,7 @@ enum {
GEVENT_22,
GEVENT_23,
};
+#define GPIO_2_EVENT GEVENT_8
#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE)
#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE