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-rw-r--r--src/soc/intel/apollolake/Kconfig1
-rw-r--r--src/soc/intel/apollolake/include/soc/meminit.h14
-rw-r--r--src/soc/intel/apollolake/meminit.c17
3 files changed, 27 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index dc639a237c..a65bb6d7a8 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
select COLLECT_TIMESTAMPS
select COMMON_FADT
+ select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
select GENERIC_GPIO_LIB
select HAVE_INTEL_FIRMWARE
select HAVE_SMI_HANDLER
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index 45b20a0989..339d2b1fac 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -69,6 +69,20 @@ enum {
LP4_16Gb_DENSITY,
};
+/*
+ * ODT settings :
+ * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A, and HIGH for ODT_B,
+ * choose ODT_AB_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A,
+ * and LOW for ODT_B, choose ODT_AB_HIGH_LOW.
+ *
+ * Note that the enum values correspond to the interpreted UPD fields
+ * witihn Ch[3:0]_OdtConfig parameters.
+*/
+enum {
+ ODT_A_B_HIGH_LOW = 0 << 1,
+ ODT_A_B_HIGH_HIGH = 1 << 1,
+};
+
/* Provide bit swizzling per DQS and byte swapping within a channel. */
struct lpddr4_chan_swizzle_cfg {
uint8_t dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS];
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 9546c19086..0a696746a3 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -73,11 +73,12 @@ static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
cfg->Ch2_Option = 0x3;
cfg->Ch3_Option = 0x3;
- /* Weak on-die termination. */
- cfg->Ch0_OdtConfig = 0;
- cfg->Ch1_OdtConfig = 0;
- cfg->Ch2_OdtConfig = 0;
- cfg->Ch3_OdtConfig = 0;
+ /* Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled
+ up to 1.1V. */
+ cfg->Ch0_OdtConfig = ODT_A_B_HIGH_HIGH;
+ cfg->Ch1_OdtConfig = ODT_A_B_HIGH_HIGH;
+ cfg->Ch2_OdtConfig = ODT_A_B_HIGH_HIGH;
+ cfg->Ch3_OdtConfig = ODT_A_B_HIGH_HIGH;
}
void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)
@@ -319,3 +320,9 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)
mem_info->dimm_cnt = index;
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
+
+uint8_t fsp_memory_soc_version(void)
+{
+ /* Bump this value when the memory configuration parameters change. */
+ return 1;
+}