diff options
| -rw-r--r-- | src/cpu/intel/car/Makefile.inc | 0 | ||||
| -rw-r--r-- | src/cpu/intel/car/disable_cache_as_ram.c | 0 | ||||
| -rw-r--r-- | src/cpu/intel/car/post_cache_as_ram.c | 0 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b/dsdt.asl | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/acpi_tables.c | 41 |
5 files changed, 41 insertions, 9 deletions
diff --git a/src/cpu/intel/car/Makefile.inc b/src/cpu/intel/car/Makefile.inc new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/cpu/intel/car/Makefile.inc diff --git a/src/cpu/intel/car/disable_cache_as_ram.c b/src/cpu/intel/car/disable_cache_as_ram.c new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/cpu/intel/car/disable_cache_as_ram.c diff --git a/src/cpu/intel/car/post_cache_as_ram.c b/src/cpu/intel/car/post_cache_as_ram.c new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/cpu/intel/car/post_cache_as_ram.c diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 7160054bf1..5e6411ce1b 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -21,15 +21,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { - /* Define the main processor.*/ - Scope (\_PR) - { - /* Looks like the P_CNT field can't be a name or method (except - * builtins like Add()) and has to be hardcoded or generated - * into SSDT */ - Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {} - } - /* For now only define 2 power states: * - S0 which is fully on * - S5 which is soft off diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 2b536e6f18..2173a3d7cf 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -26,9 +26,46 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> +#include "i82371eb.h" extern const unsigned char AmlCode[]; +static int determine_total_number_of_cores(void) +{ + device_t cpu; + int count = 0; + for(cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { + continue; + } + if (!cpu->enabled) { + continue; + } + count++; + } + return count; +} + +void generate_cpu_entries(void) +{ + int len; + int len_pr; + int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; + int numcpus = determine_total_number_of_cores(); + printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus); + + /* without the outer scope, furhter ssdt addition will end up + * within the processor statement */ + len = acpigen_write_scope("\\_PR"); + for (cpu=0; cpu < numcpus; cpu++) { + len_pr = acpigen_write_processor(cpu, pcontrol_blk, plen); + acpigen_patch_len(len_pr - 1); + len += len_pr; + } + acpigen_patch_len(len - 1); +} + unsigned long __attribute__((weak)) acpi_fill_slit(unsigned long current) { // Not implemented @@ -57,6 +94,10 @@ unsigned long __attribute__((weak)) acpi_fill_ssdt_generator(unsigned long curre const char *oem_table_id) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); + /* generate_cpu_entries() generates weird bytecode and has to come + * last or else the following entries will end up inside the + * processor scope */ + generate_cpu_entries(); return (unsigned long) acpigen_get_current(); } |