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-rw-r--r--src/soc/intel/baytrail/chip.h1
-rw-r--r--src/soc/intel/baytrail/ramstage.c13
2 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 97b92efb99..ecf1ce3da9 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -88,6 +88,7 @@ struct soc_intel_baytrail_config {
uint16_t gpu_pipeb_light_off_delay;
uint16_t gpu_pipeb_power_cycle_delay;
int gpu_pipeb_pwm_freq_hz;
+ int disable_ddr_2x_refresh_rate;
};
extern struct chip_operations soc_intel_baytrail_ops;
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 6c2de111dc..8b6d93cbe0 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -38,6 +38,7 @@
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/ramstage.h>
+#include <soc/iosf.h>
/* Global PATTRS */
DEFINE_PATTRS;
@@ -170,12 +171,24 @@ static void s3_resume_prepare(void)
s3_save_acpi_wake_source(gnvs);
}
+static void baytrail_enable_2x_refresh_rate(void)
+{
+ u32 reg;
+ reg = iosf_dunit_read(0x8);
+ reg = reg & ~0x7000;
+ reg = reg | 0x2000;
+ iosf_dunit_write(0x8, reg);
+}
+
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config)
{
struct soc_gpio_config *gpio_config;
fill_in_pattrs();
+ if (!config->disable_ddr_2x_refresh_rate)
+ baytrail_enable_2x_refresh_rate();
+
/* Allow for SSE instructions to be executed. */
write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);