diff options
101 files changed, 97 insertions, 242 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 1ed721f7e0..986c68afc4 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -15,10 +15,6 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x0 - # FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better # yet be dropped completely. config MAX_PHYSICAL_CPUS diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 18a19fc030..686025fda3 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -25,9 +25,6 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) -/* Leave some space for global variable to pass to RAM stage. */ -#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE - /* For CAR with Fam10h. */ #define CacheSizeAPStack 0x400 /* 1K */ @@ -348,7 +345,7 @@ fam10_end_part1: rep stosl /* Set up the stack pointer. */ - movl $(CacheBase + CacheSize - GlobalVarSize), %eax + movl $(CacheBase + CacheSize), %eax movl %eax, %esp post_code(0xa3) @@ -358,7 +355,7 @@ CAR_FAM10_ap: /* * Need to set stack pointer for AP. * It will be from: - * CacheBase + (CacheSize - GlobalVarSize) / 2 + * CacheBase + CacheSize / 2 * - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack * So need to get the NodeID and CoreID at first. * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need @@ -392,7 +389,7 @@ roll_cfg: /* Calculate stack pointer. */ movl $CacheSizeAPStack, %eax mull %ebx - movl $(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp + movl $(CacheBase + CacheSize / 2), %esp subl %eax, %esp /* Retrive init detected. */ diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 2aa4f302d3..861948ff57 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -164,12 +164,6 @@ static void post_cache_as_ram(void) set_sysinfo_in_ram(1); // So other core0 could start to train mem -#if CONFIG_MEM_TRAIN_SEQ == 1 -// struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - // wait for ap memory to trained -// wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c -#endif /*copy and execute coreboot_ram */ copy_and_run(0); /* We will not return */ diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index c5bdb4a5f8..23192f1a06 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -19,10 +19,6 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x04000 - config UDELAY_IO bool default n diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index e34e6f7e20..4ad28a74a6 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -32,7 +32,7 @@ void cpus_ready_for_init(void) { #if CONFIG_MEM_TRAIN_SEQ == 1 - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // wait for ap memory to trained wait_all_core0_mem_trained(sysinfox); #endif diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index 1dbf6526b7..2704876b8f 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -21,8 +21,4 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - endif # CPU_AMD_SOCKET_940 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 284c1812c9..b5090b908e 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -31,8 +31,4 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - endif diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index dcc3ba5180..dc674d8c40 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -84,7 +84,7 @@ void soft_reset(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 5980ca2a2e..b62b91f4ae 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -79,7 +79,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 84b08e6179..35d59648e6 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -72,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 96514b1856..2a6f4eacd5 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 39070eaae7..50821f994a 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -73,7 +73,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index d48b69d24a..9dd35bd9d4 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index edf931ac54..febf265113 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -31,10 +31,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index fe37842093..7385b658d3 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -67,9 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = - (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index 1e5e625e93..26fa45f2be 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -38,10 +38,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x8 diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index 84561d6b1a..710eae8d03 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -41,11 +41,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + - CONFIG_DCACHE_RAM_SIZE - - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = &sysinfo_car; // in CACHE + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct node_core_id id; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index a70baaaa2c..db8cdb0bae 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; - struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 09447a63c1..b016e5d56a 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -190,7 +190,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 9919cce880..6e0ad25f10 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index 5f5f93bebf..c94e69b64c 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -35,10 +35,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index d3717f1f35..828bbc9756 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -139,7 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 96260bc0c0..1f0d2e9175 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -31,10 +31,6 @@ config DCACHE_RAM_SIZE hex default 0x4000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x1000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 3c4f640b6a..1f8da48258 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -153,8 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index 80efbf62c8..8159a432d6 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -31,10 +31,6 @@ config DCACHE_RAM_SIZE hex default 0x4000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x1000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 014c5b03cd..c78e63ee4e 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -153,8 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index ff11218188..28c2c81642 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -30,10 +30,6 @@ config DCACHE_RAM_SIZE hex default 0x4000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x1000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index a0963da3e8..18e840c3f1 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -124,8 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; sio_init(); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 08b06803e5..088b6bf9b7 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -52,10 +52,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index aedd5cdb4a..601f542ab5 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -98,8 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM1, DIMM3, 0, 0, /* Channel B (DIMM_B1, DIMM_B2) */ }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 0ee9058f44..8a3a69877e 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -50,10 +50,6 @@ config DCACHE_RAM_SIZE hex default 0x4000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 681ffcb2ec..0ccec58b60 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -132,8 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = - (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 731e0de079..61ffd9abbe 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -35,10 +35,6 @@ config DCACHE_RAM_SIZE hex default 0x4000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x1000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index db6d2c80b3..451cb33ec3 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -230,8 +230,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = - (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; it8712f_24mhz_clkin(); it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 50bbfcac06..07c2de36e4 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 1fe7b49512..10aa14a67e 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 22d87b37bc..9884dc2180 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -85,7 +85,7 @@ void soft_reset(void) #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 366723580a..e12c235a9b 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -85,7 +85,7 @@ void soft_reset(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index 01a7cc3e04..b953b6e1c6 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -29,10 +29,6 @@ config DCACHE_RAM_SIZE hex default 0x01000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index 7c33e60809..c535294c89 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -32,10 +32,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index 28be373b4b..54caf37caa 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -62,8 +62,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = &sysinfo_car; // in CACHE + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct node_core_id id; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index d9a133bb8b..9a3a79b786 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -118,8 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + - CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 7a2fdfe572..daae829478 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -36,10 +36,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index 670f63b614..04f456ce30 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -60,8 +60,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = &sysinfo_car; // in CACHE + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct node_core_id id; diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 2622b6246c..8c36f0b09e 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -110,8 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; uint8_t tmp = 0; diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index f118c3c5c4..e2a029bad0 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -72,7 +72,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index f118c3c5c4..e2a029bad0 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -72,7 +72,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 4f9082342e..233875aada 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -76,7 +76,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 97e1e30603..60ffb19fcd 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -101,8 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) RC1|DIMM1, RC1|DIMM3, 0, 0, #endif }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index 6f491f278e..bee23f7553 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE hex default 0x04000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x8 diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 7decb72a71..e3c397c57d 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -134,8 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index a1dd681144..32abeec96a 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x04000 - config APIC_ID_OFFSET hex default 0 diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 443fa4e87b..c32728b497 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -101,7 +101,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 2bb9db483d..5cfc6cd142 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -28,10 +28,6 @@ config DCACHE_RAM_SIZE hex default 0x1000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index e93cb7e544..c79d2c0f84 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -28,10 +28,6 @@ config DCACHE_RAM_SIZE hex default 0x1000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 431883140c..56058b59fb 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -78,7 +78,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 31468176b0..bb235d683d 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -82,8 +82,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index f2de54a9e9..27152a68d9 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -83,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index eae16d35b9..5ac8508494 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -83,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 338c7f3774..34f0c2f0ca 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -83,7 +83,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index f7386660fb..fad9d7f1dc 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -75,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 4b11ea9bfa..efabd512f1 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index e05f74ea33..276ec891ee 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -49,10 +49,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */ - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */ + struct sys_info *sysinfo = &sysinfo_car; /* in CACHE */ + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); /* in RAM */ struct node_core_id id; id = get_node_core_id_x(); diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 0a97960985..dd0be1ffba 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -112,8 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index d2c4f87679..dc19d98cfc 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE hex default 0x04000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x8 diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index f53246508d..6e1a364dcc 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -103,8 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + - CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f5a1457147..d5716323a3 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -32,10 +32,6 @@ config DCACHE_RAM_SIZE hex default 0x04000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 7cccc89656..36858497a7 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -128,8 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) unsigned bsp_apicid = 0; int needs_reset; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 19f74e76fb..852efd44be 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -35,10 +35,6 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x04000 - # Define to 0 because the IRQ slot count is # determined dynamically for this board. config IRQ_SLOT_COUNT diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 0431e977ef..2bf7f1337a 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -107,7 +107,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; u8 reg; msr_t msr; diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 7d60ecfef2..3eae434de4 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index 5d0fa6bf94..7b292a8fcc 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -58,8 +58,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = &sysinfo_car; // in CACHE + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct node_core_id id; diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 18a1ff06e1..41ce82eb9b 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -111,8 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 3ea9419c0e..758884c926 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 219b82a1d0..221ccb2dbf 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -36,10 +36,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index 2e9c5a9029..4717e24e5a 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -65,8 +65,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = &sysinfo_car; // in CACHE + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 6f156bc39f..84771781c3 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -178,8 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) RC1 | DIMM5, RC1 | DIMM7, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index 9fd8c7ccf8..3cc296a985 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -34,10 +34,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index d04775bba3..d577061cd5 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -65,8 +65,8 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = &sysinfo_car; // in CACHE + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index e3113d85dc..62cbf0f7ec 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -107,8 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 20a0082b44..94b56eaa1d 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x04000 - config RAMBASE hex default 0x200000 diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index be5a8e1874..b01cd03ed9 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -109,8 +109,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + - CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 134a25ebc6..6ba6130119 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -32,10 +32,6 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x04000 - config RAMBASE hex default 0x200000 diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 28efb1cf87..aa65a96540 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -160,8 +160,7 @@ static void write_GPIO(void) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 6ad1484462..7aac4afd45 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -86,7 +86,7 @@ static int spd_read_byte(u32 device, u32 address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = { RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0, //RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0, diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 57cb3f23a8..bb8a3b1e0d 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -74,7 +74,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index ed133daf6e..4453f84455 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -72,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 67b89d1c4b..f653478756 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE hex default 0x08000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x01000 - config APIC_ID_OFFSET hex default 0x10 diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index fc7df821f2..e48d899829 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -56,8 +56,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = &sysinfo_car; // in CACHE + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct node_core_id id; diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index fc5d65966d..2423117c5e 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -112,8 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE - + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 9a38836e6f..085148fcd3 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -33,10 +33,6 @@ config DCACHE_RAM_SIZE hex default 0x0c000 -config DCACHE_RAM_GLOBAL_VAR_SIZE - hex - default 0x04000 - config APIC_ID_OFFSET hex default 0 diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 16d3c472bd..bc01aeaa8e 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -113,7 +113,7 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; msr_t msr; diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 87c2d8c0e9..14efa9792e 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -134,7 +134,7 @@ unsigned long acpi_fill_slit(unsigned long current) /* fill the first 8 byte with that num */ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); u8 *ln = sysinfox->ln; diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 712c98638e..4c06463ab9 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1098,6 +1098,10 @@ struct sys_info { } __attribute__((packed)); +#ifdef __PRE_RAM__ +extern struct sys_info sysinfo_car; +#endif + #ifndef __PRE_RAM__ device_t get_node_pci(u32 nodeid, u32 fn); #endif diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 7f05b46aa5..971051f76a 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -773,7 +773,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) u32 hole_sizek; u32 one_DCT; - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct mem_info *meminfo; meminfo = &sysinfox->meminfo[node_id]; @@ -1056,7 +1056,7 @@ static void amdfam10_domain_set_resources(device_t dev) #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) { - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct mem_info *meminfo; meminfo = &sysinfox->meminfo[i]; sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes); diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 973384bb78..2bafde617b 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -120,6 +120,9 @@ static void print_t(const char *strval) #endif /* DDR2 */ +#include <cpu/x86/car.h> +struct sys_info sysinfo_car CAR_GLOBAL; + int mctRead_SPD(u32 smaddr, u32 reg) { return spd_read_byte(smaddr, reg); @@ -128,7 +131,7 @@ int mctRead_SPD(u32 smaddr, u32 reg) void mctSMBhub_Init(u32 node) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); activate_spd_rom(ctrl); } @@ -137,7 +140,7 @@ void mctSMBhub_Init(u32 node) void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) { int j; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = &sysinfo_car; struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); for(j=0;j<DIMM_SOCKETS;j++) { diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index 769f5980ba..bfeee0ecc5 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -518,6 +518,10 @@ struct sys_info { uint32_t sbbusn; } __attribute__((packed)); +#ifdef __PRE_RAM__ +extern struct sys_info sysinfo_car; +#endif + #include <reset.h> #if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \ diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97cd3..0e0f9f4e32 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -262,4 +262,8 @@ struct sys_info { uint32_t sbbusn; } __attribute__((packed)); +#ifdef __PRE_RAM__ +extern struct sys_info sysinfo_car; +#endif + #endif /* AMDK8_PRE_F_H */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 7db338b42a..33a3245644 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -14,6 +14,9 @@ #include "option_table.h" #endif +#include <cpu/x86/car.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 86c409f949..7114e95cbe 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -39,6 +39,9 @@ #endif +#include <cpu/x86/car.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index fdec120b50..870c7c9692 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -2089,7 +2089,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 - struct sys_info *sysinfox = (void*)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (void *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) { @@ -2100,7 +2100,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); #else - memcpy(sysinfo, sysinfox, CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + memcpy(sysinfo, sysinfox, sizeof(*sysinfo)); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if !CONFIG_AP_CODE_IN_CAR |