diff options
47 files changed, 41 insertions, 70 deletions
diff --git a/src/Kconfig b/src/Kconfig index 8df5323cf6..2e06299af3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1177,9 +1177,7 @@ config BOOTBLOCK_CUSTOM # src/lib/bootblock.c#main() C entry point. bool -config C_ENVIRONMENT_BOOTBLOCK - # To be selected by arch or platform if a C environment is available during the - # bootblock. Normally this signifies availability of RW memory (e.g. SRAM). +config ROMCC_BOOTBLOCK bool ############################################################################### diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 1eed2de4d0..ed838a5b2b 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -4,7 +4,6 @@ config ARCH_ARM config ARCH_BOOTBLOCK_ARM bool select ARCH_ARM - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM bool diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 96a23dc41b..588e8cea6d 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -4,7 +4,6 @@ config ARCH_ARM64 config ARCH_BOOTBLOCK_ARM64 bool select ARCH_ARM64 - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM64 bool diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 0699e910ce..44dbb1d778 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -5,7 +5,6 @@ config ARCH_BOOTBLOCK_PPC64 bool select ARCH_PPC64 select BOOTBLOCK_CUSTOM - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_PPC64 bool diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index f2ca571c97..8369afee6d 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -77,7 +77,6 @@ config ARCH_RISCV_PMP config ARCH_BOOTBLOCK_RISCV bool default n - select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_RISCV bool diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 24a2065c0e..a788bc0e23 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -23,7 +23,7 @@ config ARCH_BOOTBLOCK_X86_32 bool default n select ARCH_X86 - select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_32 bool @@ -47,7 +47,7 @@ config ARCH_BOOTBLOCK_X86_64 bool default n select ARCH_X86 - select BOOTBLOCK_CUSTOM if !C_ENVIRONMENT_BOOTBLOCK + select BOOTBLOCK_CUSTOM if ROMCC_BOOTBLOCK config ARCH_VERSTAGE_X86_64 bool @@ -199,7 +199,7 @@ config ID_SECTION_OFFSET hex default 0x80 -# 64KiB default bootblock size when employing C_ENVIRONMENT_BOOTBLOCK. +# 64KiB default bootblock size config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 @@ -239,7 +239,7 @@ config ROMSTAGE_DEBUG_SPINLOOP choice prompt "Bootblock behaviour" default BOOTBLOCK_SIMPLE - depends on !C_ENVIRONMENT_BOOTBLOCK + depends on ROMCC_BOOTBLOCK config BOOTBLOCK_SIMPLE bool "Always load fallback" diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6f47e884a4..423c35116b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -116,7 +116,7 @@ bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-y += id.S $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h -ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) bootblock-y += bootblock_crt0.S @@ -128,7 +128,7 @@ endif bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S -else # !C_ENVIRONMENT_BOOTBLOCK +else # ROMCC_BOOTBLOCK # x86-specific linker flags ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) @@ -178,7 +178,7 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(filter-out %.ld,$(bootblock-objs)) \ -T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld) -endif # C_ENVIRONMENT_BOOTBLOCK +endif # ROMCC_BOOTBLOCK endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 @@ -223,7 +223,9 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c # gdt_init.S is included by entry32.inc when romstage is the first C # environment. -romstage-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += gdt_init.S +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +romstage-y += gdt_init.S +endif romstage-y += cbmem.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index d9d6d4ecef..9d6f5a42b4 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -13,14 +13,13 @@ #include <rules.h> -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) /* - * This path is for stages that are post bootblock when employing - * CONFIG_C_ENVIRONMENT_BOOTBLOCK. The gdt is reloaded to accommodate - * platforms that are executing out of CAR. In order to continue with - * C code execution one needs to set stack pointer and clear CAR_GLOBAL - * variables that are stage specific. + * This path is for stages that are post bootblock. The gdt is reloaded + * to accommodate platforms that are executing out of CAR. In order to + * continue with C code execution one needs to set stack pointer and + * clear .bss variables that are stage specific. */ .section ".text._start", "ax", @progbits .global _start diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 9fcb5c4e4a..325673162c 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -11,8 +11,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * This is the modern bootblock. It is used by platforms which select - * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * This is the modern bootblock. It prepares the system for C environment runtime * setup. The actual setup is done by hardware-specific code. * * It provides a bootflow similar to other architectures, and thus is considered diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S index 05b34c6c5a..7d6f42f08a 100644 --- a/src/arch/x86/bootblock_romcc.S +++ b/src/arch/x86/bootblock_romcc.S @@ -20,7 +20,7 @@ * - timestamp.inc: store TSC in MMX registers * - generated/bootblock.inc: ROMCC part of the bootblock * - * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it + * This is used on platforms which select ROMCC_BOOTBLOCK, and it * tries to do the absolute minimum before walking CBFS and jumping to romstage. * * This file assembles the bootblock program by the order of the includes. Thus, diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 3680250993..483a908816 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -36,7 +36,7 @@ /* Stack for CAR stages. Since it persists across all stages that * use CAR it can be reused. The chipset/SoC is expected to provide * the stack size. */ -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; . += CONFIG_DCACHE_BSP_STACK_SIZE; _ecar_stack = .; @@ -90,7 +90,7 @@ _ebss = .; _car_unallocated_start = .; -#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if CONFIG(ROMCC_BOOTBLOCK) _car_stack = .; _ecar_stack = _car_region_end; #endif @@ -121,6 +121,6 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC #if CONFIG(PAGING_IN_CACHE_AS_RAM) _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); #endif -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); #endif diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index e0e3ca1972..50d636b1f6 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -288,9 +288,8 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) #define asmlinkage __attribute__((regparm(0))) /* - * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() - * is the symbol jumped to for each stage after bootblock using - * cache-as-ram. + * When not using a romcc bootblock the car_stage_entry() is the symbol + * jumped to for each stage after bootblock using cache-as-ram. */ asmlinkage void car_stage_entry(void); diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 9fd9889911..f8ae9f3918 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -49,8 +49,7 @@ SECTIONS #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK - /* This is for C_ENVIRONMENT_BOOTBLOCK. arch/x86/bootblock.ld contains - * the logic for the romcc linking. */ + /* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */ BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, CONFIG_C_ENV_BOOTBLOCK_SIZE) diff --git a/src/console/Kconfig b/src/console/Kconfig index b90823ecd0..9151a32a11 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,7 +5,7 @@ config NO_BOOTBLOCK_CONSOLE config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on C_ENVIRONMENT_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE + depends on !ROMCC_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE default y help Use console during the bootblock if supported diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index cd6972062c..5a668c42df 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -29,7 +29,7 @@ _cache_as_ram_setup: bootblock_pre_c_entry: -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) movl $cache_as_ram, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ #endif diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index a3487dbe34..23df701e08 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -18,7 +18,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if !CONFIG(ROMCC_BOOTBLOCK) #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" #endif diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 9d196356e3..1f8eb9a10e 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -71,8 +71,8 @@ static void romstage_main(unsigned long bist) /* We do not return here. */ } -#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK) -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, +#if CONFIG(ROMCC_BOOTBLOCK) +/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK * keeping changes in cache_as_ram.S easy to manage. */ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig index b78389215d..73afe0bb45 100644 --- a/src/cpu/intel/microcode/Kconfig +++ b/src/cpu/intel/microcode/Kconfig @@ -1,7 +1,7 @@ config MICROCODE_UPDATE_PRE_RAM bool depends on SUPPORT_CPU_UCODE_IN_CBFS - default y if C_ENVIRONMENT_BOOTBLOCK + default y if !ROMCC_BOOTBLOCK help Select this option if you want to update the microcode during the cache as ram setup. diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index f316329552..e31260588e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON_TIMEBASE select PARALLEL_MP select NO_FIXED_XIP_ROM_SIZE - select C_ENVIRONMENT_BOOTBLOCK config SMM_TSEG_SIZE hex diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 10001bdc5f..00af79a440 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -27,6 +27,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE + select ROMCC_BOOTBLOCK config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index a2ebeb2325..176ae9e08a 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM - select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 7504233bda..e6025b5653 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -21,5 +21,4 @@ config CPU_QEMU_X86 select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE - select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 9e00c55a92..e0babd5a5a 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,7 +29,7 @@ #include <arch/rom_segs.h> -#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \ +#if !CONFIG(ROMCC_BOOTBLOCK) || \ CONFIG(SIPI_VECTOR_IN_ROM) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 85ebd831ea..efb5fa96e9 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -77,7 +77,7 @@ config XIP_ROM_SIZE config SETUP_XIP_CACHE bool - depends on C_ENVIRONMENT_BOOTBLOCK + depends on !ROMCC_BOOTBLOCK depends on !NO_XIP_EARLY_STAGES help Select this option to set up an MTRR to cache XIP stages loaded diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index dc0c46d460..b444ea3c86 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -268,7 +268,9 @@ postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c postcar-$(CONFIG_GENERIC_UDELAY) += timer.c # Use program.ld for all the platforms which use C fo the bootblock. -bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += program.ld +endif decompressor-y += program.ld postcar-y += program.ld diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index e1e129a97d..50dba252fe 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,7 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA select CBMEM_TOP_BACKUP + select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index c0df2a1abd..4fbcd4aad4 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -18,6 +18,7 @@ config NORTHBRIDGE_AMD_PI default y if CPU_AMD_PI default n select CBMEM_TOP_BACKUP + select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 4877fa9d6b..69b055e96c 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index aad2674241..6dc4ef03d7 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_SETTINGS select INTEL_DDI select INTEL_GMA_ACPI - select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE if NORTHBRIDGE_INTEL_HASWELL diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index a0550ec3c7..c22275a6b1 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841336..a119b817ae 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -21,7 +21,6 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP - select C_ENVIRONMENT_BOOTBLOCK if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index edf4f2321e..73060363f5 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config VGA_BIOS_ID string diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 2a54e2495e..247686ade3 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP - select C_ENVIRONMENT_BOOTBLOCK config CBFS_SIZE hex diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index df1b7e478a..a829443098 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -95,7 +95,7 @@ config VBOOT_VBNV_FLASH config VBOOT_STARTS_IN_BOOTBLOCK bool default n - depends on C_ENVIRONMENT_BOOTBLOCK + depends on !ROMCC_BOOTBLOCK help Firmware verification happens during the end of or right after the bootblock. This implies that a static VBOOT2_WORK() buffer must be diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5f9792b28a..e192818a0b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,7 +49,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_S3 - select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -82,7 +81,6 @@ config DCACHE_RAM_SIZE default 0x10000 config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK hex default 0x4000 help diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0d6f2ff0bc..cbf88df902 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -69,7 +69,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 - select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP @@ -98,7 +97,6 @@ config DCACHE_RAM_SIZE default 0x10000 config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK hex default 0x4000 help diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 026f6da669..0b3b30a4f8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -38,7 +38,6 @@ config CPU_SPECIFIC_OPTIONS select ACPI_NHLT select SOC_INTEL_COMMON_NHLT # Misc options - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 397e86768c..fac14cbd3b 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select ROMCC_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 7ea01863ae..f08b58982a 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -46,7 +46,6 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select C_ENVIRONMENT_BOOTBLOCK config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 095ed988c6..07bcf22b1d 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select NO_FIXED_XIP_ROM_SIZE - select C_ENVIRONMENT_BOOTBLOCK config PCIEXP_ASPM bool diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5731cff916..5c91ac142f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -58,7 +58,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_COMMON diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index cb3713d3b0..0ce0d5bdd1 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select PLATFORM_USES_FSP2_0 - select C_ENVIRONMENT_BOOTBLOCK select IOAPIC select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a2fe5ed3da..7f1cd893a3 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 461d230371..099c7ddc9d 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,7 +26,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select C_ENVIRONMENT_BOOTBLOCK select NO_MMCONF_SUPPORT select REG_SCRIPT select PLATFORM_USES_FSP2_0 @@ -226,11 +225,6 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. -##### -# Bootblock -# The following options support the C_ENVIRONMENT_BOOTBLOCK. -##### - config DCACHE_BSP_STACK_SIZE hex default 0x4000 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f5f1e30aaa..032ded4025 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -30,7 +30,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING - select C_ENVIRONMENT_BOOTBLOCK select FSP_M_XIP select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2824e52558..9c5fc984c9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES - select C_ENVIRONMENT_BOOTBLOCK select CACHE_MRC_SETTINGS select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 9fb83707bf..bc502c9d53 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -276,7 +276,7 @@ void verified_boot_early_check(void) { printk(BIOS_SPEW, "%s: processing early items\n", __func__); - if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK) && + if (CONFIG(ROMCC_BOOTBLOCK) && CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)) { printk(BIOS_SPEW, "%s: check the manifest\n", __func__); if (verified_boot_check_manifest() != 0) |