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-rw-r--r--src/soc/nvidia/tegra210/ccplex.c17
-rw-r--r--src/soc/nvidia/tegra210/include/soc/clk_rst.h3
2 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c
index f3c61cbbe6..a3c67225c0 100644
--- a/src/soc/nvidia/tegra210/ccplex.c
+++ b/src/soc/nvidia/tegra210/ccplex.c
@@ -92,9 +92,26 @@ static void request_ram_repair(void)
stopwatch_duration_usecs(&sw));
}
+static void set_cpu_ack_width(uint32_t val)
+{
+ uint32_t reg;
+
+ reg = read32(CLK_RST_REG(cpu_softrst_ctrl2));
+ reg &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
+ reg |= val;
+ write32(CLK_RST_REG(cpu_softrst_ctrl2), reg);
+}
+
void ccplex_cpu_prepare(void)
{
enable_cpu_clocks();
+
+ /*
+ * The POR value of CAR2PMC_CPU_ACK_WIDTH is 0x200.
+ * The recommended value is 0.
+ */
+ set_cpu_ack_width(0);
+
enable_cpu_power_partitions();
mainboard_configure_pmc();
diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h
index 817a041422..87790d5fb1 100644
--- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h
+++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h
@@ -534,6 +534,9 @@ enum {
#define PCLK_DIVISOR_SHIFT 0
#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT)
+/* CPU_SOFTRST_CTRL2_0 0x388 */
+#define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff
+
/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)