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-rw-r--r--src/southbridge/amd/sr5650/early_setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index d91f3bdd90..ec555f81b2 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -1,6 +1,7 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -437,7 +438,6 @@ static void sr5650_por_htiu_index_init(device_t nb_dev)
set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<2, 0x1<<2);
set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<4, 0x1<<4);
- set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 0 << 21);
axindxc_reg(0x10, 1 << 9, 1 << 9);
set_pcie_enable_bits(nb_dev, 0x10 | 5 << 16, 1 << 9, 1 << 9);
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<26, 0x1<<26);