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-rw-r--r--src/soc/intel/apollolake/acpi.c3
-rw-r--r--src/soc/intel/apollolake/acpi/globalnvs.asl1
-rw-r--r--src/soc/intel/apollolake/include/soc/nvs.h3
3 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index c950255e73..d24416fd6c 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -144,6 +144,9 @@ unsigned long southbridge_write_acpi_tables(device_t device,
static void acpi_create_gnvs(struct global_nvs_t *gnvs)
{
+ if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
+ gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
+
if (IS_ENABLED(CONFIG_CHROMEOS)) {
/* Initialize Verified Boot data */
chromeos_init_vboot(&gnvs->chromeos);
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index e081dcb60b..1799f315ab 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -33,6 +33,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
LIDS, 8, // 0x03 - LID State
PWRS, 8, // 0x04 - AC Power State
DPTE, 8, // 0x05 - Enable DPTF
+ CBMC, 32, // 0x06 - 0x09 - Coreboot Memory Console
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 4768aaabe4..a7ddf77f6d 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -33,7 +33,8 @@ struct global_nvs_t {
uint8_t lids; /* 0x03 - LID State */
uint8_t pwrs; /* 0x04 - AC Power State */
uint8_t dpte; /* 0x05 - Enable DPTF */
- uint8_t unused[251];
+ uint32_t cbmc; /* 0x06 - 0x09 - Coreboot Memory Console */
+ uint8_t unused[247];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;