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-rw-r--r--src/soc/intel/cannonlake/Kconfig5
-rw-r--r--src/soc/intel/cannonlake/chip.h4
2 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index c06b91eb48..e524275b8f 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -183,6 +183,11 @@ config MAX_ROOT_PORTS
default 24 if SOC_INTEL_CANNONLAKE_PCH_H
default 16
+config MAX_PCIE_CLOCKS
+ int
+ default 16 if SOC_INTEL_CANNONLAKE_PCH_H
+ default 6
+
config SMM_TSEG_SIZE
hex
default 0x800000
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index b17df4b21b..f34528a017 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -168,10 +168,10 @@ struct soc_intel_cannonlake_config {
/* PCIe output clocks type to Pcie devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
- uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
+ uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */
- uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
+ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
/* PCIe LTR(Latency Tolerance Reporting) mechanism */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* Enable/Disable HotPlug support for Root Port */