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-rw-r--r--src/soc/intel/skylake/romstage/power_state.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 78650fa590..3eae936337 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -44,7 +44,8 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
* S5 because the PCH does not set the WAK_STS bit when waking
* from a true G3 state.
*/
- if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
+ if (!(ps->pm1_sts & WAK_STS) &&
+ (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)))
prev_sleep_state = ACPI_S5;
/*