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-rw-r--r--src/mainboard/asrock/g41c-gs/romstage.c3
-rw-r--r--src/mainboard/foxconn/g41s-k/romstage.c3
-rw-r--r--src/mainboard/gigabyte/ga-g41m-es2l/romstage.c3
-rw-r--r--src/mainboard/intel/dg43gt/romstage.c3
-rw-r--r--src/northbridge/intel/x4x/early_init.c7
-rw-r--r--src/southbridge/intel/i82801jx/i82801jx.h1
6 files changed, 8 insertions, 12 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index dd885db94d..24a5cfde39 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -87,9 +87,6 @@ void mainboard_romstage_entry(unsigned long bist)
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
- /* Disable watchdog timer */
- RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
-
/* Set southbridge and Super I/O GPIOs. */
ich7_enable_lpc();
mb_lpc_setup();
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 2a704a3c66..ba07e45e99 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -91,9 +91,6 @@ void mainboard_romstage_entry(unsigned long bist)
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
- /* Disable watchdog timer. */
- RCBA32(GCS) = RCBA32(GCS) | 0x20;
-
/* Set up southbridge and Super I/O GPIOs. */
ich7_enable_lpc();
mb_lpc_setup();
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 67d3eb1310..e71e00cf52 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -140,9 +140,6 @@ void mainboard_romstage_entry(unsigned long bist)
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
- /* Disable watchdog timer */
- RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
-
/* Set southbridge and Super I/O GPIOs. */
ich7_enable_lpc();
mb_gpio_init();
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 6944b1819e..d3b2b6aec4 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -75,9 +75,6 @@ void mainboard_romstage_entry(unsigned long bist)
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
- /* Disable watchdog timer */
- RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
-
/* Set southbridge and Super I/O GPIOs. */
ich10_enable_lpc();
mb_gpio_init();
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 27fe9162f0..fbdbcb4496 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -58,6 +58,13 @@ void x4x_early_init(void)
pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
+ printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
+ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
+ outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */
+ outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */
+ outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */
+ printk(BIOS_DEBUG, " done.\n");
+
if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
/* Enable internal GFX */
pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 9b0f95593b..88e0ad01f3 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -166,6 +166,7 @@
#define RCBA_RPFN 0x0238
#define RCBA_DMC 0x2010
#define RCBA_HPTC 0x3404
+#define GCS 0x3410
#define RCBA_BUC 0x3414
#define RCBA_FD 0x3418 /* Function Disable, see below. */
#define RCBA_CG 0x341c