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-rw-r--r--src/mainboard/intel/bayleybay_fsp/devicetree.cb20
-rw-r--r--src/mainboard/intel/minnowmax/devicetree.cb20
-rw-r--r--src/soc/intel/fsp_baytrail/chip.h20
-rw-r--r--src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c50
4 files changed, 55 insertions, 55 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index 356c8df5f3..a19a676804 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -24,16 +24,16 @@ chip soc/intel/fsp_baytrail
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
#### FSP register settings ####
- register "SataMode" = "SATA_MODE_AHCI"
- register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
- register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
- register "MrcInitTsegSize" = "TSEG_SIZE_8_MB"
- register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
- register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
- register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
- register "ApertureSize" = "APERTURE_SIZE_DEFAULT"
- register "GttSize" = "GTT_SIZE_DEFAULT"
- register "LpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
+ register "PcdSataMode" = "SATA_MODE_AHCI"
+ register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
+ register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
+ register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB"
+ register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
+ register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
+ register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
+ register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
+ register "PcdGttSize" = "GTT_SIZE_DEFAULT"
+ register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb
index a0ac7ae74a..dd999a09e0 100644
--- a/src/mainboard/intel/minnowmax/devicetree.cb
+++ b/src/mainboard/intel/minnowmax/devicetree.cb
@@ -24,16 +24,16 @@ chip soc/intel/fsp_baytrail
register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
#### FSP register settings ####
- register "SataMode" = "SATA_MODE_AHCI"
- register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
- register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
- register "MrcInitTsegSize" = "TSEG_SIZE_8_MB"
- register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
- register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
- register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
- register "ApertureSize" = "APERTURE_SIZE_DEFAULT"
- register "GttSize" = "GTT_SIZE_DEFAULT"
- register "LpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
+ register "PcdSataMode" = "SATA_MODE_AHCI"
+ register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
+ register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
+ register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB"
+ register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
+ register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
+ register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"
+ register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT"
+ register "PcdGttSize" = "GTT_SIZE_DEFAULT"
+ register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE"
register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED"
diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h
index 7e868629f3..12eba10e8b 100644
--- a/src/soc/intel/fsp_baytrail/chip.h
+++ b/src/soc/intel/fsp_baytrail/chip.h
@@ -31,8 +31,8 @@ struct soc_intel_fsp_baytrail_config {
/* ***** UPD Configuration ***** */
/* Spd addresses */
- uint8_t MrcInitSPDAddr1;
- uint8_t MrcInitSPDAddr2;
+ uint8_t PcdMrcInitSPDAddr1;
+ uint8_t PcdMrcInitSPDAddr2;
#define SPD_ADDR_DEFAULT 0x00
#define SPD_ADDR_DISABLED 0xFF
@@ -44,7 +44,7 @@ struct soc_intel_fsp_baytrail_config {
* 0x0 "IDE"
* 0x1 "AHCI"
*/
- uint8_t SataMode;
+ uint8_t PcdSataMode;
#define SATA_MODE_DEFAULT 0x00
#define SATA_MODE_IDE 0x01
#define SATA_MODE_AHCI 0x02
@@ -56,7 +56,7 @@ struct soc_intel_fsp_baytrail_config {
* 0x04, "4 MB"
* 0x08, "8 MB"
*/
- uint16_t MrcInitTsegSize;
+ uint16_t PcdMrcInitTsegSize;
#define TSEG_SIZE_DEFAULT 0
#define TSEG_SIZE_1_MB 1
#define TSEG_SIZE_2_MB 2
@@ -69,7 +69,7 @@ struct soc_intel_fsp_baytrail_config {
* 0x600, "1.5 GB"
* 0x800, "2.0 GB"
*/
- uint16_t MrcInitMmioSize;
+ uint16_t PcdMrcInitMmioSize;
#define MMIO_SIZE_DEFAULT 0x00
#define MMIO_SIZE_1_0_GB 0x400
#define MMIO_SIZE_1_5_GB 0x600
@@ -86,7 +86,7 @@ struct soc_intel_fsp_baytrail_config {
* 0x2 "eMMC 4.1"
* 0x3 "eMMC 4.5"
*/
- uint8_t eMMCBootMode;
+ uint8_t PcdeMMCBootMode;
#define EMMC_USE_DEFAULT 0
#define EMMC_DISABLED 1
#define EMMC_AUTO 2
@@ -113,7 +113,7 @@ struct soc_intel_fsp_baytrail_config {
* 0x0F, "480 MB"
* 0x10, "512 MB"
*/
- uint8_t IgdDvmt50PreAlloc;
+ uint8_t PcdIgdDvmt50PreAlloc;
#define IGD_MEMSIZE_DEFAULT 0x00
#define IGD_MEMSIZE_32MB 0x01
#define IGD_MEMSIZE_64MB 0x02
@@ -138,7 +138,7 @@ struct soc_intel_fsp_baytrail_config {
* Selection 0x2 , "256 MB"
* Selection 0x3 , "512 MB"
*/
- uint8_t ApertureSize;
+ uint8_t PcdApertureSize;
#define APERTURE_SIZE_DEFAULT 0
#define APERTURE_SIZE_128MB 1
#define APERTURE_SIZE_256MB 2
@@ -149,7 +149,7 @@ struct soc_intel_fsp_baytrail_config {
* Selection 0x1 , "1 MB"
* Selection 0x2 , "2 MB"
*/
- uint8_t GttSize;
+ uint8_t PcdGttSize;
#define GTT_SIZE_DEFAULT 0
#define GTT_SIZE_1MB 1
#define GTT_SIZE_2MB 2
@@ -158,7 +158,7 @@ struct soc_intel_fsp_baytrail_config {
* Enable PCI Mode for LPSS SIO devices.
* If disabled, LPSS SIO devices will run in ACPI mode.
*/
- uint8_t LpssSioEnablePciMode;
+ uint8_t PcdLpssSioEnablePciMode;
#define LPSS_PCI_MODE_DEFAULT 0x00
#define LPSS_PCI_MODE_DISABLE 0x01
#define LPSS_PCI_MODE_ENABLE 0x02
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 82f83a9632..2a41e612a3 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -82,49 +82,49 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig;
/* Set SPD addresses */
- if (config->MrcInitSPDAddr1 == SPD_ADDR_DISABLED)
+ if (config->PcdMrcInitSPDAddr1 == SPD_ADDR_DISABLED)
UpdData->PcdMrcInitSPDAddr1 = 0x00;
- else if (config->MrcInitSPDAddr1 != SPD_ADDR_DEFAULT)
- UpdData->PcdMrcInitSPDAddr1 = config->MrcInitSPDAddr1;
+ else if (config->PcdMrcInitSPDAddr1 != SPD_ADDR_DEFAULT)
+ UpdData->PcdMrcInitSPDAddr1 = config->PcdMrcInitSPDAddr1;
printk(BIOS_DEBUG, "SPD Addr1:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr1);
- if (config->MrcInitSPDAddr2 == SPD_ADDR_DISABLED)
+ if (config->PcdMrcInitSPDAddr2 == SPD_ADDR_DISABLED)
UpdData->PcdMrcInitSPDAddr2 = 0x00;
- else if (config->MrcInitSPDAddr2 != SPD_ADDR_DEFAULT)
- UpdData->PcdMrcInitSPDAddr2 = config->MrcInitSPDAddr2;
+ else if (config->PcdMrcInitSPDAddr2 != SPD_ADDR_DEFAULT)
+ UpdData->PcdMrcInitSPDAddr2 = config->PcdMrcInitSPDAddr2;
printk(BIOS_DEBUG, "SPD Addr2:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr2);
- if (config->SataMode != SATA_MODE_DEFAULT)
- UpdData->PcdSataMode = config->SataMode - SATA_MODE_IDE;
+ if (config->PcdSataMode != SATA_MODE_DEFAULT)
+ UpdData->PcdSataMode = config->PcdSataMode - SATA_MODE_IDE;
- if ((config->eMMCBootMode != EMMC_USE_DEFAULT) ||
- (config->eMMCBootMode != EMMC_FOLLOWS_DEVICETREE))
- UpdData->PcdeMMCBootMode = config->eMMCBootMode;
+ if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) ||
+ (config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE))
+ UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode;
- if (config->LpssSioEnablePciMode != LPSS_PCI_MODE_DEFAULT)
- UpdData->PcdLpssSioEnablePciMode = config->LpssSioEnablePciMode -
+ if (config->PcdLpssSioEnablePciMode != LPSS_PCI_MODE_DEFAULT)
+ UpdData->PcdLpssSioEnablePciMode = config->PcdLpssSioEnablePciMode -
LPSS_PCI_MODE_DISABLE;
- if (config->MrcInitTsegSize != TSEG_SIZE_DEFAULT)
- UpdData->PcdMrcInitTsegSize = config->MrcInitTsegSize;
+ if (config->PcdMrcInitTsegSize != TSEG_SIZE_DEFAULT)
+ UpdData->PcdMrcInitTsegSize = config->PcdMrcInitTsegSize;
printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize);
- if (config->MrcInitMmioSize != MMIO_SIZE_DEFAULT)
- UpdData->PcdMrcInitMmioSize = config->MrcInitMmioSize;
+ if (config->PcdMrcInitMmioSize != MMIO_SIZE_DEFAULT)
+ UpdData->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize);
- if (config->IgdDvmt50PreAlloc != IGD_MEMSIZE_DEFAULT)
- UpdData->PcdIgdDvmt50PreAlloc = config->IgdDvmt50PreAlloc;
+ if (config->PcdIgdDvmt50PreAlloc != IGD_MEMSIZE_DEFAULT)
+ UpdData->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc;
printk(BIOS_DEBUG, "IGD Memory Size:\t%d MB\n",
UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER);
- if (config->ApertureSize != APERTURE_SIZE_DEFAULT)
- UpdData->PcdApertureSize = config->ApertureSize;
+ if (config->PcdApertureSize != APERTURE_SIZE_DEFAULT)
+ UpdData->PcdApertureSize = config->PcdApertureSize;
printk(BIOS_DEBUG, "Aperture Size:\t\t%d MB\n",
APERTURE_SIZE_BASE << UpdData->PcdApertureSize);
- if (config->GttSize != GTT_SIZE_DEFAULT)
- UpdData->PcdGttSize = config->GttSize;
+ if (config->PcdGttSize != GTT_SIZE_DEFAULT)
+ UpdData->PcdGttSize = config->PcdGttSize;
printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize);
/* Advance dev to PCI device 0.0 */
@@ -152,7 +152,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
break;
case EMMC_DEV_FUNC: /* EMMC 4.1*/
if ((dev->enabled) &&
- (config->eMMCBootMode == EMMC_FOLLOWS_DEVICETREE))
+ (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE))
UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED;
break;
case SDIO_DEV_FUNC:
@@ -190,7 +190,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
break;
case MMC45_DEV_FUNC: /* MMC 4.5*/
if ((dev->enabled) &&
- (config->eMMCBootMode == EMMC_FOLLOWS_DEVICETREE))
+ (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE))
UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED;
break;
case SIO_DMA1_DEV_FUNC:
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-06 13:13:52 +0000