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-rw-r--r--src/soc/intel/apollolake/chip.c7
-rw-r--r--src/soc/intel/apollolake/chip.h6
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h10
3 files changed, 21 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 9ee6dbb96d..e6904da75f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -567,6 +567,13 @@ static void glk_fsp_silicon_init_params_cb(
* has set up. Hence skipping in FSP.
*/
silconfig->SkipSpiPCP = 1;
+
+ /*
+ * FSP provides UPD interface to execute IPC command. In order to
+ * improve boot performance, configure PmicPmcIpcCtrl for PMC to program
+ * PMIC PCH_PWROK delay.
+ */
+ silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl;
#endif
}
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 8ad622f684..202f2acf1e 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -156,6 +156,12 @@ struct soc_intel_apollolake_config {
* (1) Power
* (2) Power & Performance */
enum pnp_settings pnp_settings;
+
+ /* PMIC PCH_PWROK delay configuration - IPC Configuration
+ * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
+ * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
+ */
+ uint32_t PmicPmcIpcCtrl;
};
typedef struct soc_intel_apollolake_config config_t;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
index cc194b2240..18a43e2b8f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
@@ -1715,9 +1715,15 @@ typedef struct {
**/
UINT8 SkipSpiPCP;
-/** Offset 0x03AB
+/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration
+ Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset
+ (23:16) + OR Value (15:8) + AND Value (7:0)
**/
- UINT8 ReservedFspsUpd[5];
+ UINT32 PmicPmcIpcCtrl;
+
+/** Offset 0x03AF
+**/
+ UINT8 ReservedFspsUpd[1];
} FSP_S_CONFIG;
/** Fsp S SGX Configuration