diff options
| -rw-r--r-- | src/soc/intel/tigerlake/acpi.c | 26 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/cpu.c | 36 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/cpu.h | 20 |
3 files changed, 20 insertions, 62 deletions
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 58c8e9ccf1..ac296ed945 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -53,70 +53,70 @@ enum { static const acpi_cstate_t cstate_map[NUM_C_STATES] = { [C_STATE_C0] = {}, [C_STATE_C1] = { - .latency = 0, + .latency = C1_LATENCY, .power = C1_POWER, .resource = MWAIT_RES(0, 0), }, [C_STATE_C1E] = { - .latency = 0, + .latency = C1_LATENCY, .power = C1_POWER, .resource = MWAIT_RES(0, 1), }, [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C6_LATENCY, .power = C6_POWER, .resource = MWAIT_RES(2, 0), }, [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C6_LATENCY, .power = C6_POWER, .resource = MWAIT_RES(2, 1), }, [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 0), }, [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 1), }, [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 2), }, [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 3), }, [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C8_LATENCY, .power = C8_POWER, .resource = MWAIT_RES(4, 0), }, [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C9_LATENCY, .power = C9_POWER, .resource = MWAIT_RES(5, 0), }, [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C10_LATENCY, .power = C10_POWER, .resource = MWAIT_RES(6, 0), }, }; static int cstate_set_non_s0ix[] = { - C_STATE_C1E, + C_STATE_C1, C_STATE_C6_LONG_LAT, C_STATE_C7S_LONG_LAT }; static int cstate_set_s0ix[] = { - C_STATE_C1E, + C_STATE_C1, C_STATE_C7S_LONG_LAT, C_STATE_C10 }; diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d33194e4c9..64ba2f9909 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -144,39 +144,6 @@ static void set_energy_perf_bias(u8 policy) wrmsr(IA32_ENERGY_PERF_BIAS, msr); } -static void configure_c_states(void) -{ - msr_t msr; - - /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); - - /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); - - /* C-state Interrupt Response Latency Control 3 - package C8 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); - - /* C-state Interrupt Response Latency Control 4 - package C9 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); - - /* C-state Interrupt Response Latency Control 5 - package C10 */ - msr.hi = 0; - msr.lo = IRTL_VALID | IRTL_32768_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; - wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -190,9 +157,6 @@ void soc_core_init(struct device *cpu) enable_lapic_tpr(); setup_lapic(); - /* Configure c-state interrupt response time */ - configure_c_states(); - /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h index 0d8e17f49b..b52a0c4bfd 100644 --- a/src/soc/intel/tigerlake/include/soc/cpu.h +++ b/src/soc/intel/tigerlake/include/soc/cpu.h @@ -6,13 +6,13 @@ #include <intelblocks/msr.h> -/* Latency times in units of 32768ns */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d +/* Latency times in us */ +#define C1_LATENCY 1 +#define C6_LATENCY 127 +#define C7_LATENCY 253 +#define C8_LATENCY 260 +#define C9_LATENCY 487 +#define C10_LATENCY 1048 /* Power in units of mW */ #define C1_POWER 0x3e8 @@ -25,12 +25,6 @@ /* Common Timer Copy (CTC) frequency - 38.4MHz. */ #define CTC_FREQ 38400000 -#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ - (((1 << ((base)*5)) * (limit)) / 1000) -#define C_STATE_LATENCY_FROM_LAT_REG(reg) \ - C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) - /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); |