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-rw-r--r--src/mainboard/ocp/sonorapass/Makefile.inc1
-rw-r--r--src/mainboard/ocp/sonorapass/romstage.c28
2 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc
index 8501868fbf..9bd017393c 100644
--- a/src/mainboard/ocp/sonorapass/Makefile.inc
+++ b/src/mainboard/ocp/sonorapass/Makefile.inc
@@ -1 +1,2 @@
bootblock-y += bootblock.c
+romstage-y += romstage.c
diff --git a/src/mainboard/ocp/sonorapass/romstage.c b/src/mainboard/ocp/sonorapass/romstage.c
new file mode 100644
index 0000000000..1acd8c3964
--- /dev/null
+++ b/src/mainboard/ocp/sonorapass/romstage.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+ void *start = (void *) m_cfg;
+
+ // BoardId
+ *((uint8_t *) (start + 140)) = 0x1d;
+ // BoardTypeBitmask
+ *((uint32_t *) (start + 104)) = 0x11111111;
+ // DebugPrintLevel
+ *((uint8_t *) (start + 45)) = 8;
+ // KtiLinkSpeedMode
+ *((uint8_t *) (start + 64)) = 0;
+ // mmiolSize
+ *((uint32_t *) (start + 88)) = 0;
+ // mmiohBase
+ *((uint32_t *) (start + 92)) = 0x2000;
+ // KtiPrefetchEn
+ *((uint8_t *) (start + 53)) = 2;
+ // KtiFpgaEnable
+ *((uint8_t *) (start + 55)) = 0;
+ *((uint8_t *) (start + 56)) = 0;
+}