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-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb4
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb4
2 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index e8dc7bd8cb..85f9e51084 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -117,10 +117,6 @@ chip soc/intel/tigerlake
# Enable S0ix
register "s0ix_enable" = "1"
- # D3Hot and D3Cold for TCSS
- register "TcssD3HotEnable" = "1"
- register "TcssD3ColdEnable" = "1"
-
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index ef8de3cb2d..5c275b3951 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -113,10 +113,6 @@ chip soc/intel/tigerlake
# Enable S0ix
register "s0ix_enable" = "1"
- # D3Hot and D3Cold for TCSS
- register "TcssD3HotEnable" = "1"
- register "TcssD3ColdEnable" = "1"
-
#HD Audio
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHdaEnable" = "0"