diff options
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index b80cd82d50..c3223b1913 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -67,6 +67,9 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 9a0ab64672..4bada02fc8 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -65,6 +65,9 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |