diff options
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e60e648ef9..4492acb7ea 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -37,6 +37,9 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 1f05e0ee46..643db36c2c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -37,6 +37,9 @@ chip soc/intel/tigerlake register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1" + register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[3]" = "3" |