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-rw-r--r--src/soc/intel/cannonlake/chip.h3
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index fd37d26492..752ec1f315 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -242,6 +242,9 @@ struct soc_intel_cannonlake_config {
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
+ /* Enables support for Teton Glacier hybrid storage device */
+ uint8_t TetonGlacierMode;
+
/* PL1 Override value in Watts */
uint32_t tdp_pl1_override;
/* PL2 Override value in Watts */
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index f1b8446f48..80918f12d9 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -374,6 +374,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
#endif
params->Device4Enable = config->Device4Enable;
+ /* Teton Glacier hybrid storage support */
+ params->TetonGlacierMode = config->TetonGlacierMode;
+
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced */