summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--Documentation/mainboard/index.md2
-rw-r--r--Documentation/mainboard/supermicro/x11-lga1151-series/index.md7
-rw-r--r--Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md (renamed from Documentation/mainboard/supermicro/x11ssh-tf.md)6
-rw-r--r--Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf_flash.jpg (renamed from Documentation/mainboard/supermicro/x11ssh_flash.jpg)bin138435 -> 138435 bytes
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/Kconfig (renamed from src/mainboard/supermicro/x11ssh/Kconfig)42
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/Kconfig.name3
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/Makefile.inc (renamed from src/mainboard/supermicro/x11ssh/Makefile.inc)0
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/acpi/ec.asl (renamed from src/mainboard/supermicro/x11ssh/acpi/ec.asl)0
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/acpi/mainboard.asl (renamed from src/mainboard/supermicro/x11ssh/acpi/mainboard.asl)0
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/acpi/superio.asl (renamed from src/mainboard/supermicro/x11ssh/acpi/superio.asl)0
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/acpi_tables.c (renamed from src/mainboard/supermicro/x11ssh/acpi_tables.c)0
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/board_info.txt2
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/bootblock.c (renamed from src/mainboard/supermicro/x11ssh/bootblock.c)2
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/cmos.layout (renamed from src/mainboard/supermicro/x11ssh/cmos.layout)0
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/devicetree.cb240
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/dsdt.asl (renamed from src/mainboard/supermicro/x11ssh/dsdt.asl)0
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/ramstage.c (renamed from src/mainboard/supermicro/x11ssh/ramstage.c)2
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/romstage.c (renamed from src/mainboard/supermicro/x11ssh/romstage.c)0
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/board_info.txt (renamed from src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt)3
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h (renamed from src/mainboard/supermicro/x11ssh/gpio.h)6
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb103
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd (renamed from src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd)0
-rw-r--r--src/mainboard/supermicro/x11ssh/Kconfig.name3
-rw-r--r--src/mainboard/supermicro/x11ssh/board_info.txt6
-rw-r--r--src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb290
25 files changed, 389 insertions, 328 deletions
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 2745a7165d..ea476eb59f 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -108,7 +108,7 @@ The boards in this section are not real mainboards, but emulators.
## Supermicro
- [X10SLM+-F](supermicro/x10slm-f.md)
-- [X11SSH-TF](supermicro/x11ssh-tf.md)
+- [X11 LGA1151 series](supermicro/x11-lga1151-series/index.md)
## UP
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/index.md b/Documentation/mainboard/supermicro/x11-lga1151-series/index.md
new file mode 100644
index 0000000000..79d2571009
--- /dev/null
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/index.md
@@ -0,0 +1,7 @@
+# X11 LGA1151 series
+
+The supermicros X11 series with socket LGA1151 are mostly the same boards with some minor
+differences in internal and external interfaces like available PCIe slots, 1 GbE, 10 GbE,
+IPMI etc. This is why those boards are grouped as "X11 LGA1151 series".
+
+- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
diff --git a/Documentation/mainboard/supermicro/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
index 16e70d4a9f..79e7f3e5eb 100644
--- a/Documentation/mainboard/supermicro/x11ssh-tf.md
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
@@ -15,7 +15,7 @@ The CH341 was found working, while Dediprog won't detect the chip.
For more details have a look at the [flashing tutorial].
The flash IC can be found between the two PCIe slots near the southbridge:
-![](x11ssh_flash.jpg)
+![](x11ssh-tf_flash.jpg)
## BMC (IPMI)
@@ -68,6 +68,6 @@ mainboard near the [AST2400]. This chip is an [MX25L25635F].
[flashrom]: https://flashrom.org/Flashrom
[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
-[flashing tutorial]: ../../flash_tutorial/ext_power.md
-[Intel FSP2.0]: ../../soc/intel/fsp/index.md
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
+[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
diff --git a/Documentation/mainboard/supermicro/x11ssh_flash.jpg b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf_flash.jpg
index 8ab07f23c7..8ab07f23c7 100644
--- a/Documentation/mainboard/supermicro/x11ssh_flash.jpg
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf_flash.jpg
Binary files differ
diff --git a/src/mainboard/supermicro/x11ssh/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig
index dcf6bb9533..54be4e0104 100644
--- a/src/mainboard/supermicro/x11ssh/Kconfig
+++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig
@@ -1,4 +1,4 @@
-config BOARD_SUPERMICRO_BASEBOARD_X11SSH
+config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
def_bool n
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_RESUME
@@ -12,7 +12,27 @@ config BOARD_SUPERMICRO_BASEBOARD_X11SSH
select GENERATE_SMBIOS_TABLES
select IPMI_KCS
-if BOARD_SUPERMICRO_BASEBOARD_X11SSH
+if BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
+
+config MAINBOARD_FAMILY
+ string
+ default "Supermicro_X11_LGA1151_SERIES"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF
+
+config MAINBOARD_DIR
+ string
+ default "supermicro/x11-lga1151-series"
+
+config VARIANT_DIR
+ string
+ default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config VBOOT
select VBOOT_NO_BOARD_SUPPORT
@@ -40,22 +60,6 @@ config IRQ_SLOT_COUNT
int
default 18
-config MAINBOARD_DIR
- string
- default "supermicro/x11ssh"
-
-config VARIANT_DIR
- string
- default "tf" if BOARD_SUPERMICRO_X11SSH_TF
-
-config DEVICETREE
- string
- default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
-
-config MAINBOARD_PART_NUMBER
- string
- default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF
-
config MAX_CPUS
int
default 8
@@ -76,4 +80,4 @@ config DIMM_SPD_SIZE
int
default 512
-endif # BOARD_SUPERMICRO_BASEBOARD_X11SSH
+endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name
new file mode 100644
index 0000000000..ec01b135f8
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig.name
@@ -0,0 +1,3 @@
+config BOARD_SUPERMICRO_X11SSH_TF
+ bool "X11SSH-TF"
+ select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
diff --git a/src/mainboard/supermicro/x11ssh/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc
index a6d789e11c..a6d789e11c 100644
--- a/src/mainboard/supermicro/x11ssh/Makefile.inc
+++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc
diff --git a/src/mainboard/supermicro/x11ssh/acpi/ec.asl b/src/mainboard/supermicro/x11-lga1151-series/acpi/ec.asl
index e69de29bb2..e69de29bb2 100644
--- a/src/mainboard/supermicro/x11ssh/acpi/ec.asl
+++ b/src/mainboard/supermicro/x11-lga1151-series/acpi/ec.asl
diff --git a/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl b/src/mainboard/supermicro/x11-lga1151-series/acpi/mainboard.asl
index e69de29bb2..e69de29bb2 100644
--- a/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl
+++ b/src/mainboard/supermicro/x11-lga1151-series/acpi/mainboard.asl
diff --git a/src/mainboard/supermicro/x11ssh/acpi/superio.asl b/src/mainboard/supermicro/x11-lga1151-series/acpi/superio.asl
index e69de29bb2..e69de29bb2 100644
--- a/src/mainboard/supermicro/x11ssh/acpi/superio.asl
+++ b/src/mainboard/supermicro/x11-lga1151-series/acpi/superio.asl
diff --git a/src/mainboard/supermicro/x11ssh/acpi_tables.c b/src/mainboard/supermicro/x11-lga1151-series/acpi_tables.c
index e69de29bb2..e69de29bb2 100644
--- a/src/mainboard/supermicro/x11ssh/acpi_tables.c
+++ b/src/mainboard/supermicro/x11-lga1151-series/acpi_tables.c
diff --git a/src/mainboard/supermicro/x11-lga1151-series/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/board_info.txt
new file mode 100644
index 0000000000..2fa11c95be
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/board_info.txt
@@ -0,0 +1,2 @@
+Category: server
+Vendor name: Supermicro
diff --git a/src/mainboard/supermicro/x11ssh/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c
index 8bc8ab00e5..27653f5ae0 100644
--- a/src/mainboard/supermicro/x11ssh/bootblock.c
+++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c
@@ -15,7 +15,7 @@
#include <bootblock_common.h>
#include <soc/gpio.h>
-#include "gpio.h"
+#include <variant/gpio.h>
#include <superio/aspeed/common/aspeed.h>
#include <superio/aspeed/ast2400/ast2400.h>
#include <delay.h>
diff --git a/src/mainboard/supermicro/x11ssh/cmos.layout b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout
index 201ca3320c..201ca3320c 100644
--- a/src/mainboard/supermicro/x11ssh/cmos.layout
+++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
new file mode 100644
index 0000000000..a5ff0c5df0
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -0,0 +1,240 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s5_enable_ac" = "0"
+ register "deep_s5_enable_dc" = "0"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # FSP Configuration
+ register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
+ register "ScsSdCardEnabled" = "0"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "SaGv" = "SaGv_Disabled"
+
+ # Disable SGX
+ register "sgx_enable" = "0" # SGX is broken in coreboot
+ register "PrmrrSize" = "128 * MiB"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # SATA configuration
+ register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
+ register "EnableSata" = "1"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable" = "{ \
+ [0] = 1, \
+ [1] = 1, \
+ [2] = 1, \
+ [3] = 1, \
+ [4] = 1, \
+ [5] = 1, \
+ [6] = 1, \
+ [7] = 1, \
+ }"
+
+ register "SataPortsDevSlp" = "{\
+ [0] = 0, \
+ [1] = 0, \
+ [2] = 0, \
+ [3] = 0, \
+ [4] = 0, \
+ [5] = 0, \
+ [6] = 0, \
+ [7] = 0, \
+ }"
+
+ # superspeed_inter-chip_supplement (SSIC) disabled
+ register "SsicPortEnable" = "0"
+
+ # USB configuration
+ # USB2/3
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+
+ # ?
+ register "usb2_ports[14]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[15]" = "USB2_PORT_MID(OC0)"
+
+ # USB4/5
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"
+
+ # USB0/1
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
+
+ # USB9/10 (USB3.0)
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"
+ register "usb2_ports[12]" = "USB2_PORT_MID(OC3)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
+
+ # USB6/7 (USB3.0)
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC4)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
+
+ # USB8 (USB3.0)
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC5)"
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
+
+ # IPMI USB HUB
+ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
+
+ # LPC
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
+ register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
+ register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
+ register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
+
+ # VR Settings Configuration for 4 Domains
+ # ICC_MAX = 0 (Auto)
+ # Voltage limit 1.52V (not used on KBL-S and KBL-DT)
+ # Disable PS4 powerstate in S0ix, thus no package C10 support
+ # psi threshold is using FSP default values
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1, \
+ .psi4enable = 0, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0, \
+ .voltage_limit = 1520 \
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1, \
+ .psi4enable = 0, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0, \
+ .voltage_limit = 1520 \
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1, \
+ .psi4enable = 0, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0 ,\
+ .voltage_limit = 1520 \
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1, \
+ .psi4enable = 0, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0, \
+ .voltage_limit = 1520 \
+ }"
+
+ # No extra VR mailbox command
+ register "SendVrMbxCmd" = "0"
+
+ # Lock Down
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 01.0 off end # CPU PCIe Port 10 (x16)
+ device pci 01.1 off end # CPU PCIe Port 11 (x8)
+ device pci 01.2 off end # CPU PCIe Port 12 (x4)
+ device pci 02.0 off end # Integrated Graphics Device (IGD)
+ device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 off end # Imaging Unit
+ device pci 08.0 off end # Gaussion Mixture Model (GMM)
+ device pci 13.0 off end # Integrated Sensor Hub
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # I2C #4
+ device pci 1b.0 off end # PCH PCIe Port 17
+ device pci 1b.1 off end # PCH PCIe Port 18
+ device pci 1b.2 off end # PCH PCIe Port 19
+ device pci 1b.3 off end # PCH PCIe Port 20
+ device pci 1c.0 off end # PCH PCIe Port 1
+ device pci 1c.1 off end # PCH PCIe Port 2
+ device pci 1c.2 off end # PCH PCIe Port 3
+ device pci 1c.3 off end # PCH PCIe Port 4
+ device pci 1c.4 off end # PCH PCIe Port 5
+ device pci 1c.5 off end # PCH PCIe Port 6
+ device pci 1c.6 off end # PCH PCIe Port 7
+ device pci 1c.7 off end # PCH PCIe Port 8
+ device pci 1d.0 off end # PCH PCIe Port 9
+ device pci 1d.1 off end # PCH PCIe Port 10
+ device pci 1d.2 off end # PCH PCIe Port 11
+ device pci 1d.3 off end # PCH PCIe Port 12
+ device pci 1d.4 off end # PCH PCIe Port 13
+ device pci 1d.5 off end # PCH PCIe Port 14
+ device pci 1d.6 off end # PCH PCIe Port 15
+ device pci 1d.7 off end # PCH PCIe Port 16
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # SPI #0
+ device pci 1f.0 on # LPC Interface
+ chip superio/common
+ device pnp 2e.0 on end
+ end
+ chip drivers/pc80/tpm # TPM
+ device pnp 0c31.0 on end
+ end
+ end
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 off end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # SPI Controller
+ device pci 1f.6 off end # GbE
+ device pci 1f.7 off end # Intel Trace Hub
+ end
+end
diff --git a/src/mainboard/supermicro/x11ssh/dsdt.asl b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl
index ac929a6bc4..ac929a6bc4 100644
--- a/src/mainboard/supermicro/x11ssh/dsdt.asl
+++ b/src/mainboard/supermicro/x11-lga1151-series/dsdt.asl
diff --git a/src/mainboard/supermicro/x11ssh/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c
index a37d2d2430..694165aefc 100644
--- a/src/mainboard/supermicro/x11ssh/ramstage.c
+++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c
@@ -13,7 +13,7 @@
#include <bootstate.h>
#include <soc/ramstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
diff --git a/src/mainboard/supermicro/x11ssh/romstage.c b/src/mainboard/supermicro/x11-lga1151-series/romstage.c
index cb1f1059f2..cb1f1059f2 100644
--- a/src/mainboard/supermicro/x11ssh/romstage.c
+++ b/src/mainboard/supermicro/x11-lga1151-series/romstage.c
diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/board_info.txt
index f3eb3ef227..893ccf436c 100644
--- a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/board_info.txt
@@ -1,6 +1,7 @@
+Category: server
Vendor name: Supermicro
Board name: X11SSH-TF
-Category: server
+Board URL: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
diff --git a/src/mainboard/supermicro/x11ssh/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
index 02fe90c34d..a5eed6bd13 100644
--- a/src/mainboard/supermicro/x11ssh/gpio.h
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
@@ -13,8 +13,8 @@
* GNU General Public License for more details.
*/
-#ifndef _GPIOX11SSHTF_H
-#define _GPIOX11SSHTF_H
+#ifndef _GPIO_X11SSH_TF_H
+#define _GPIO_X11SSH_TF_H
#include <soc/gpe.h>
#include <soc/gpio.h>
@@ -245,4 +245,4 @@ static const struct pad_config early_gpio_table[] = {
};
#endif /* __ACPI__ */
-#endif /* _GPIOX11SSHTF_H */
+#endif /* _GPIO_X11SSH_TF_H */
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
new file mode 100644
index 0000000000..1039f7a0ca
--- /dev/null
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
@@ -0,0 +1,103 @@
+chip soc/intel/skylake
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ register "gen1_dec" = "0x007c0a01" # Super IO SWC
+ register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+ register "gen3_dec" = "0x000c03e1" # UART3
+ register "gen4_dec" = "0x000c02e1" # UART4
+
+ # PCIe configuration
+ # Enable JPCIE1
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "0"
+
+ # Enable ASpeed PCI bridge
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpClkReqSupport[2]" = "0"
+
+ # Enable X550T (10GbE)
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "0"
+
+ # Enable M.2
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "0"
+
+ device domain 0 on
+ device pci 01.0 on end # unused
+ device pci 01.1 on # PCIE Slot (JPCIE1)
+ smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
+ end
+ device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1)
+ smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
+ end
+ device pci 1c.2 on # PCI Express Port 3
+ device pci 00.0 on # Aspeed PCI Bridge
+ device pci 00.0 on end # Aspeed 2400 VGA
+ end
+ end
+ device pci 1c.4 on # PCI Express Port 5
+ device pci 00.0 on end # 10GbE
+ device pci 00.1 on end # 10GbE
+ end
+ device pci 1d.0 on # PCI Express Port 9
+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
+ end
+ device pci 1f.0 on # LPC Interface
+ chip drivers/ipmi
+ # On cold boot it takes a while for the BMC to start the IPMI service
+ register "wait_for_bmc" = "1"
+ register "bmc_boot_timeout" = "60"
+ device pnp ca2.0 on end # IPMI KCS
+ end
+ chip superio/common
+ device pnp 2e.0 on
+ chip superio/aspeed/ast2400
+ device pnp 2e.2 on # SUART1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # SUART2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.4 on # SWC
+ io 0x60 = 0xa00
+ io 0x62 = 0xa10
+ io 0x64 = 0xa20
+ io 0x66 = 0xa30
+ irq 0x70 = 0xb
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 0xc
+ end
+ device pnp 2e.7 on end # GPIO
+ device pnp 2e.b on # SUART3
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.c on # SUART4
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.d on end # iLPC2AHB
+ device pnp 2e.e on # Mailbox
+ io 0x60 = 0xa40
+ irq 0x70 = 0x00
+ end
+ end
+ end
+ end
+ end
+ end
+end
diff --git a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd
index a29568072e..a29568072e 100644
--- a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd
+++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro-rwab.fmd
diff --git a/src/mainboard/supermicro/x11ssh/Kconfig.name b/src/mainboard/supermicro/x11ssh/Kconfig.name
deleted file mode 100644
index 43d0517378..0000000000
--- a/src/mainboard/supermicro/x11ssh/Kconfig.name
+++ /dev/null
@@ -1,3 +0,0 @@
-config BOARD_SUPERMICRO_X11SSH_TF
- bool "X11SSH-TF"
- select BOARD_SUPERMICRO_BASEBOARD_X11SSH
diff --git a/src/mainboard/supermicro/x11ssh/board_info.txt b/src/mainboard/supermicro/x11ssh/board_info.txt
deleted file mode 100644
index 029d2a9bbb..0000000000
--- a/src/mainboard/supermicro/x11ssh/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Supermicro
-Board name: X11SSH Baseboard
-Category: server
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
deleted file mode 100644
index ce6bfa5fba..0000000000
--- a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb
+++ /dev/null
@@ -1,290 +0,0 @@
-chip soc/intel/skylake
-
- # Enable deep Sx states
- register "deep_s5_enable_ac" = "0"
- register "deep_s5_enable_dc" = "0"
- register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
-
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- register "gpe0_dw0" = "GPP_B"
- register "gpe0_dw1" = "GPP_D"
- register "gpe0_dw2" = "GPP_E"
-
- register "gen1_dec" = "0x007c0a01" # Super IO SWC
- register "gen2_dec" = "0x000c0ca1" # IPMI KCS
- register "gen3_dec" = "0x000c03e1" # UART3
- register "gen4_dec" = "0x000c02e1" # UART4
-
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
- # FSP Configuration
- register "SmbusEnable" = "1"
- register "ScsEmmcEnabled" = "0"
- register "ScsEmmcHs400Enabled" = "0"
- register "ScsSdCardEnabled" = "0"
- register "SkipExtGfxScan" = "1"
- register "Device4Enable" = "1"
- register "SaGv" = "SaGv_Disabled"
-
- # Disable SGX
- register "sgx_enable" = "0" # SGX is broken in coreboot
- register "PrmrrSize" = "128 * MiB"
-
- register "pirqa_routing" = "PCH_IRQ11"
- register "pirqb_routing" = "PCH_IRQ10"
- register "pirqc_routing" = "PCH_IRQ11"
- register "pirqd_routing" = "PCH_IRQ11"
- register "pirqe_routing" = "PCH_IRQ11"
- register "pirqf_routing" = "PCH_IRQ11"
- register "pirqg_routing" = "PCH_IRQ11"
- register "pirqh_routing" = "PCH_IRQ11"
-
- # SATA configuration
- register "SataMode" = "0" # AHCI
- register "EnableSata" = "1"
- register "SataSalpSupport" = "1"
- register "SataPortsEnable" = "{ \
- [0] = 1, \
- [1] = 1, \
- [2] = 1, \
- [3] = 1, \
- [4] = 1, \
- [5] = 1, \
- [6] = 1, \
- [7] = 1, \
- }"
-
- register "SataPortsDevSlp" = "{\
- [0] = 0, \
- [1] = 0, \
- [2] = 0, \
- [3] = 0, \
- [4] = 0, \
- [5] = 0, \
- [6] = 0, \
- [7] = 0, \
- }"
-
- # superspeed_inter-chip_supplement (SSIC) disabled
- register "SsicPortEnable" = "0"
-
- # USB configuration
- register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2/3
- register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2/3
- register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # ?
- register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # ?
-
- register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB4/5
- register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # USB4/5
-
- register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB0/1
- register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # USB0/1
-
- register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
- register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0)
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"
-
- register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
- register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0)
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)"
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)"
-
- register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # USB8 (USB3.0)
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)"
-
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB
-
- # LPC
- register "serirq_mode" = "SERIRQ_CONTINUOUS"
-
- # PCIe configuration
- # Enable JPCIE1
- register "PcieRpEnable[0]" = "1"
- register "PcieRpClkReqSupport[0]" = "0"
-
- # Enable ASpeed PCI bridge
- register "PcieRpEnable[2]" = "1"
- register "PcieRpClkReqSupport[2]" = "0"
-
- # Enable X550T (10GbE)
- register "PcieRpEnable[4]" = "1"
- register "PcieRpClkReqSupport[4]" = "0"
-
- # Enable M.2
- register "PcieRpEnable[8]" = "1"
- register "PcieRpClkReqSupport[8]" = "0"
-
- # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
- # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
- register "PmConfigSlpS3MinAssert" = "0x02"
-
- # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
- register "PmConfigSlpS4MinAssert" = "0x04"
-
- # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
- register "PmConfigSlpSusMinAssert" = "0x03"
-
- # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
- register "PmConfigSlpAMinAssert" = "0x03"
-
- # VR Settings Configuration for 4 Domains
- # ICC_MAX = 0 (Auto)
- # Voltage limit 1.52V (not used on KBL-S and KBL-DT)
- # Disable PS4 powerstate in S0ix, thus no package C10 support
- # psi threshold is using FSP default values
- register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
- .psi3threshold = VR_CFG_AMP(1),
- .psi3enable = 1, \
- .psi4enable = 0, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0, \
- .voltage_limit = 1520 \
- }"
-
- register "domain_vr_config[VR_IA_CORE]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
- .psi3threshold = VR_CFG_AMP(1),
- .psi3enable = 1, \
- .psi4enable = 0, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0, \
- .voltage_limit = 1520 \
- }"
-
- register "domain_vr_config[VR_GT_UNSLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
- .psi3threshold = VR_CFG_AMP(1),
- .psi3enable = 1, \
- .psi4enable = 0, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0 ,\
- .voltage_limit = 1520 \
- }"
-
- register "domain_vr_config[VR_GT_SLICED]" = "{
- .vr_config_enable = 1, \
- .psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
- .psi3threshold = VR_CFG_AMP(1),
- .psi3enable = 1, \
- .psi4enable = 0, \
- .imon_slope = 0x0, \
- .imon_offset = 0x0, \
- .icc_max = 0, \
- .voltage_limit = 1520 \
- }"
-
- # No extra VR mailbox command
- register "SendVrMbxCmd" = "0"
-
- # Lock Down
- register "common_soc_config" = "{
- .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
- }"
-
- device cpu_cluster 0 on
- device lapic 0 on end
- end
- device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 01.0 on end # unused
- device pci 01.1 on
- smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
- end # PCIE Slot (JPCIE1)
- device pci 04.0 on end # SA thermal subsystem
- device pci 14.0 on end # USB xHCI
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # Thermal Subsystem
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 on end # Management Engine Interface 2
- device pci 17.0 on end # SATA
- device pci 1c.0 on
- smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
- end # PCI Express Port 1 (Slot JPCIE1)
- device pci 1c.2 on
- device pci 00.0 on
- device pci 00.0 on end # Aspeed 2400 VGA
- end
- end # PCI Express Port 3
- device pci 1c.4 on
- device pci 00.0 on end # 10GbE
- device pci 00.1 on end # 10GbE
- end # PCI Express Port 5
- device pci 1d.0 on
- smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
- end # PCI Express Port 9
- device pci 1f.0 on
- chip drivers/ipmi
- # On cold boot it takes a while for the BMC to start the IPMI service
- register "wait_for_bmc" = "1"
- register "bmc_boot_timeout" = "60"
- device pnp ca2.0 on end # IPMI KCS
- end
- chip superio/common
- device pnp 2e.0 on
- chip superio/aspeed/ast2400
- device pnp 2e.2 on # SUART1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # SUART2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.4 on # SWC
- io 0x60 = 0xa00
- io 0x62 = 0xa10
- io 0x64 = 0xa20
- io 0x66 = 0xa30
- irq 0x70 = 0xb
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 0xc
- end
- device pnp 2e.7 on # GPIO
- end
- device pnp 2e.b on # SUART3
- io 0x60 = 0x3e8
- irq 0x70 = 4
- end
- device pnp 2e.c on # SUART4
- io 0x60 = 0x2e8
- irq 0x70 = 3
- end
- device pnp 2e.d on # iLPC2AHB
- end
- device pnp 2e.e on # Mailbox
- io 0x60 = 0xa40
- irq 0x70 = 0x00
- end
- end
- end
- end
- chip drivers/pc80/tpm
- device pnp 0c31.0 on end
- end
- end # LPC Interface
- device pci 1f.1 on end # P2SB
- device pci 1f.2 on end # Power Management Controller
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # SPI Controller
- end
-end