summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/cpu/amd/agesa/s3_resume.c11
-rw-r--r--src/southbridge/amd/Kconfig3
2 files changed, 12 insertions, 2 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 8a9ffeea63..6ba9212ab4 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -152,10 +152,16 @@ void write_mtrr(struct spi_flash *flash, u32 *p_nvram_pos, unsigned idx)
{
msr_t msr_data;
msr_data = rdmsr(idx);
+
+#if CONFIG_AMD_SB_SPI_TX_LEN >= 8
+ flash->write(flash, *p_nvram_pos, 8, &msr_data);
+ *p_nvram_pos += 8;
+#else
flash->write(flash, *p_nvram_pos, 4, &msr_data.lo);
*p_nvram_pos += 4;
flash->write(flash, *p_nvram_pos, 4, &msr_data.hi);
*p_nvram_pos += 4;
+#endif
}
#endif
@@ -264,10 +270,11 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
nvram_pos = 0;
flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize);
- for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) {
+ for (nvram_pos = 0; nvram_pos < DataSize - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) {
data = *(u32 *) (Data + nvram_pos);
- flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos));
+ flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos));
}
+ flash->write(flash, nvram_pos + pos + 4, DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos));
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);
diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig
index 20d557307a..42209ce7b2 100644
--- a/src/southbridge/amd/Kconfig
+++ b/src/southbridge/amd/Kconfig
@@ -18,3 +18,6 @@ source src/southbridge/amd/sr5650/Kconfig
config SPI_FLASH
bool
default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA
+config AMD_SB_SPI_TX_LEN
+ int
+ default 4