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-rw-r--r--src/soc/intel/tigerlake/include/soc/pci_devs.h3
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params.c4
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index 82d8360524..cfb70cdb9f 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -34,6 +34,9 @@
#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
+#define SA_DEV_SLOT_CPU_PCIE 0x06
+#define SA_DEVFN_CPU_PCIE PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0)
+
#define SA_DEV_SLOT_TBT 0x07
#define SA_DEVFN_TBT(x) PCI_DEVFN(SA_DEV_SLOT_TBT, (x))
#define NUM_TBT_FUNCTIONS 4
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 4a45fd43ec..b12faecd24 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -217,6 +217,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* Skip CPU replacement check */
m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
+
+ /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
+ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
+ m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)