diff options
| -rw-r--r-- | src/cpu/amd/family_10h-family_15h/defaults.h | 12 | ||||
| -rw-r--r-- | src/northbridge/amd/amdfam10/misc_control.c | 6 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 7fd115c93f..28df747971 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -162,6 +162,14 @@ static const struct { 0x0000000C, 0x00000000, 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */ + { OSVW_ID_Length, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000005, 0x00000000, + 0x0000ffff, 0x00000000}, /* OSVW_ID_Length = 0x5 */ + + { OSVW_Status, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000010, 0x00000000, + 0xffffffff, 0x00000000}, /* OsvwId4 = 0x1 */ + { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL, 0x00000000, 1 << (50-32), 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/ @@ -621,6 +629,10 @@ static const struct { { 3, 0x1b8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ + /* Errata 504 workaround */ + { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00040000, 0x00040000 }, /* [18] = 1b */ + /* IBS Control Register */ { 3, 0x1cc, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */ diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 0b312b1c95..4c65bca79f 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -75,6 +75,7 @@ static void mcf3_read_resources(device_t dev) static void set_agp_aperture(device_t dev, uint32_t pci_id) { + uint32_t dword; struct resource *resource; resource = probe_resource(dev, 0x94); @@ -105,6 +106,11 @@ static void set_agp_aperture(device_t dev, uint32_t pci_id) /* Report the resource has been stored... */ report_resource_stored(pdev, resource, " <gart>"); + + /* Errata 540 workaround */ + dword = pci_read_config32(pdev, 0x90); + dword |= 0x1 << 6; /* DisGartTblWlkPrb = 0x1 */ + pci_write_config32(pdev, 0x90, dword); } } } |