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-rw-r--r--src/soc/intel/common/block/cpu/Kconfig9
-rw-r--r--src/soc/intel/common/block/cpu/Makefile.inc8
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c228
-rw-r--r--src/soc/intel/common/block/include/intelblocks/cpulib.h117
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h19
5 files changed, 380 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 7b78c53ea7..56b0064d59 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -1,3 +1,12 @@
+config SOC_INTEL_COMMON_BLOCK_CPU
+ bool
+ default n
+ help
+ This option helps to select Intel Common CPU Model support code
+ which provides various CPU related APIs which are common
+ between all Intel Processor families. Common CPU code is supported
+ for SOCs starting from SKL,KBL,APL, and future.
+
config SOC_INTEL_COMMON_BLOCK_CAR
bool
default n
diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc
index abdff2f58b..4253844582 100644
--- a/src/soc/intel/common/block/cpu/Makefile.inc
+++ b/src/soc/intel/common/block/cpu/Makefile.inc
@@ -1,3 +1,9 @@
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S
-postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
+
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
+
+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
new file mode 100644
index 0000000000..325e1bb857
--- /dev/null
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -0,0 +1,228 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <delay.h>
+#include <intelblocks/cpulib.h>
+#include <intelblocks/fast_spi.h>
+#include <lib.h>
+#include <reset.h>
+#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
+#include <intelblocks/msr.h>
+#include <soc/pci_devs.h>
+#include <stdint.h>
+
+/*
+ * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with
+ * Turbo Ratio which is the Maximum Ratio.
+ */
+void cpu_set_max_ratio(void)
+{
+ /* Check for configurable TDP option */
+ if (get_turbo_state() == TURBO_ENABLED)
+ cpu_set_p_state_to_turbo_ratio();
+}
+
+/*
+ * Get the TDP Nominal Ratio from MSR 0x648 Bits 7:0.
+ */
+u8 cpu_get_tdp_nominal_ratio(void)
+{
+ u8 nominal_ratio;
+ msr_t msr;
+
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ nominal_ratio = msr.lo & 0xff;
+ return nominal_ratio;
+}
+
+/*
+ * Read PLATFORM_INFO MSR (0xCE).
+ * Return Value of Bit 34:33 (CONFIG_TDP_LEVELS).
+ *
+ * Possible values of Bit 34:33 are -
+ * 00 : Config TDP not supported
+ * 01 : One Additional TDP level supported
+ * 10 : Two Additional TDP level supported
+ * 11 : Reserved
+ */
+int cpu_config_tdp_levels(void)
+{
+ msr_t platform_info;
+
+ /* Bits 34:33 indicate how many levels supported */
+ platform_info = rdmsr(MSR_PLATFORM_INFO);
+ return (platform_info.hi >> 1) & 3;
+}
+
+/*
+ * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the
+ * factory configured values for of 1-core, 2-core, 3-core
+ * and 4-core turbo ratio limits for all processors.
+ *
+ * 7:0 - MAX_TURBO_1_CORE
+ * 15:8 - MAX_TURBO_2_CORES
+ * 23:16 - MAX_TURBO_3_CORES
+ * 31:24 - MAX_TURBO_4_CORES
+ *
+ * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.
+ */
+void cpu_set_p_state_to_turbo_ratio(void)
+{
+ msr_t msr, perf_ctl;
+
+ msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ perf_ctl.hi = 0;
+
+ wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
+ printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
+ ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
+}
+
+/*
+ * CONFIG_TDP_NOMINAL MSR (0x648) Bits 7:0 tells Nominal
+ * TDP level ratio to be used for specific processor (in units
+ * of 100MHz).
+ *
+ * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.
+ */
+void cpu_set_p_state_to_nominal_tdp_ratio(void)
+{
+ msr_t msr, perf_ctl;
+
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ perf_ctl.hi = 0;
+
+ wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
+ printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
+ ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
+}
+
+/*
+ * PLATFORM_INFO MSR (0xCE) Bits 15:8 tells
+ * MAX_NON_TURBO_LIM_RATIO.
+ *
+ * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.
+ */
+void cpu_set_p_state_to_max_non_turbo_ratio(void)
+{
+ msr_t msr, perf_ctl;
+
+ /* Platform Info bits 15:8 give max ratio */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ perf_ctl.lo = msr.lo & 0xff00;
+ perf_ctl.hi = 0;
+
+ wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
+ printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
+ ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
+}
+
+/*
+ * Get the Burst/Turbo Mode State from MSR IA32_MISC_ENABLE 0x1A0
+ * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED.
+ * Also check for the cpuid 0x6 to check whether Burst mode unsupported.
+ */
+int cpu_get_burst_mode_state(void)
+{
+
+ msr_t msr;
+ unsigned int eax;
+ int burst_en, burst_cap, burst_state = BURST_MODE_UNKNOWN;
+
+ eax = cpuid_eax(0x6);
+ burst_cap = eax & 0x2;
+ msr = rdmsr(IA32_MISC_ENABLE);
+ burst_en = !(msr.hi & BURST_MODE_DISABLE);
+
+ if (!burst_cap && burst_en) {
+ burst_state = BURST_MODE_UNAVAILABLE;
+ } else if (burst_cap && !burst_en) {
+ burst_state = BURST_MODE_DISABLED;
+ } else if (burst_cap && burst_en) {
+ burst_state = BURST_MODE_ENABLED;
+ }
+ return burst_state;
+}
+
+/*
+ * Enable Burst mode.
+ */
+void cpu_enable_burst_mode(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.hi &= ~BURST_MODE_DISABLE;
+ wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+/*
+ * Disable Burst mode.
+ */
+void cpu_disable_burst_mode(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.hi |= BURST_MODE_DISABLE;
+ wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+/*
+ * Enable Intel Enhanced Speed Step Technology.
+ */
+void cpu_enable_eist(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+/*
+ * Disable Intel Enhanced Speed Step Technology.
+ */
+void cpu_disable_eist(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+/*
+ * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120
+ * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.
+ */
+void cpu_enable_untrusted_mode(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(MSR_POWER_MISC);
+ msr.lo |= ENABLE_IA_UNTRUSTED;
+ wrmsr(MSR_POWER_MISC, msr);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
new file mode 100644
index 0000000000..0038ecdb7a
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_CPULIB_H
+#define SOC_INTEL_COMMON_BLOCK_CPULIB_H
+
+#include <stdint.h>
+
+/*
+ * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with
+ * Turbo Ratio which is the Maximum Ratio.
+ */
+void cpu_set_max_ratio(void);
+
+/*
+ * Get the TDP Nominal Ratio from MSR 0x648 Bits 7:0.
+ */
+u8 cpu_get_tdp_nominal_ratio(void);
+
+/*
+ * Read PLATFORM_INFO MSR (0xCE).
+ * Return Value of Bit 34:33 (CONFIG_TDP_LEVELS).
+ *
+ * Possible values of Bit 34:33 are -
+ * 00 : Config TDP not supported
+ * 01 : One Additional TDP level supported
+ * 10 : Two Additional TDP level supported
+ * 11 : Reserved
+ */
+int cpu_config_tdp_levels(void);
+
+/*
+ * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the
+ * factory configured values for of 1-core, 2-core, 3-core
+ * and 4-core turbo ratio limits for all processors.
+ *
+ * 7:0 - MAX_TURBO_1_CORE
+ * 15:8 - MAX_TURBO_2_CORES
+ * 23:16 - MAX_TURBO_3_CORES
+ * 31:24 - MAX_TURBO_4_CORES
+ *
+ * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.
+ */
+void cpu_set_p_state_to_turbo_ratio(void);
+
+/*
+ * CONFIG_TDP_NOMINAL MSR (0x648) Bits 7:0 tells Nominal
+ * TDP level ratio to be used for specific processor (in units
+ * of 100MHz).
+ *
+ * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.
+ */
+void cpu_set_p_state_to_nominal_tdp_ratio(void);
+
+/*
+ * PLATFORM_INFO MSR (0xCE) Bits 15:8 tells
+ * MAX_NON_TURBO_LIM_RATIO.
+ *
+ * Set PERF_CTL MSR (0x199) P_Req (14:8 bits) with that value.
+ */
+void cpu_set_p_state_to_max_non_turbo_ratio(void);
+
+/*
+ * Get the Burst/Turbo Mode State from MSR IA32_MISC_ENABLE 0x1A0
+ * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED.
+ * Also check for the cpuid 0x6 to check whether Burst mode unsupported.
+ * Below are the possible cpu_get_burst_mode_state() return values-
+ * These states are exposed to the User since user
+ * need to know which is the current Burst Mode State.
+ */
+enum {
+ BURST_MODE_UNKNOWN,
+ BURST_MODE_UNAVAILABLE,
+ BURST_MODE_DISABLED,
+ BURST_MODE_ENABLED
+};
+int cpu_get_burst_mode_state(void);
+
+/*
+ * Enable Burst mode.
+ */
+void cpu_enable_burst_mode(void);
+
+/*
+ * Disable Burst mode.
+ */
+void cpu_disable_burst_mode(void);
+
+/*
+ * Enable Intel Enhanced Speed Step Technology.
+ */
+void cpu_enable_eist(void);
+
+/*
+ * Disable Intel Enhanced Speed Step Technology.
+ */
+void cpu_disable_eist(void);
+
+/*
+ * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120
+ * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.
+ */
+void cpu_enable_untrusted_mode(void);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 119c21526c..6d78ed8c2f 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -36,6 +36,7 @@
#define ENABLE_IA_UNTRUSTED (1 << 6)
#define FLUSH_DL1_L2 (1 << 8)
#define MSR_EMULATE_PM_TMR 0x121
+#define EMULATE_DELAY_OFFSET_VALUE 20
#define EMULATE_PM_TMR_EN (1 << 16)
#define MSR_FEATURE_CONFIG 0x13c
#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
@@ -44,8 +45,13 @@
#define SMM_MCA_CAP_MSR 0x17d
#define SMM_CPU_SVRSTR_BIT 57
#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
+#define MSR_FLEX_RATIO 0x194
+#define FLEX_RATIO_LOCK (1 << 20)
+#define FLEX_RATIO_EN (1 << 16)
#define MSR_IA32_PERF_CTL 0x199
#define IA32_MISC_ENABLE 0x1a0
+/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */
+#define BURST_MODE_DISABLE (1 << 6)
#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_PREFETCH_CTL 0x1a4
#define PREFETCH_L1_DISABLE (1 << 0)
@@ -56,8 +62,13 @@
#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7)
#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
+#define PRMRR_PHYS_MASK_MSR 0x1f5
+#define PRMRR_PHYS_MASK_LOCK (1 << 10)
+#define PRMRR_PHYS_MASK_VALID (1 << 11)
#define MSR_POWER_CTL 0x1fc
#define MSR_EVICT_CTL 0x2e0
+#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4
+#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401
#define SMM_FEATURE_CONTROL_MSR 0x4e0
@@ -98,6 +109,10 @@
#define PKG_POWER_LIMIT_CLAMP (1 << 16)
#define PKG_POWER_LIMIT_TIME_SHIFT 17
#define PKG_POWER_LIMIT_TIME_MASK (0x7f)
+/* SMM save state MSRs */
+#define SMBASE_MSR 0xc20
+#define IEDBASE_MSR 0xc22
+
#define MSR_IA32_PQR_ASSOC 0x0c8f
/* MSR bits 33:32 encode slot number 0-3 */
#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
@@ -105,5 +120,9 @@
#define MSR_IA32_L3_MASK_2 0x0c92
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
+/* MTRR_CAP_MSR bits */
+#define SMRR_SUPPORTED (1<<11)
+#define PRMRR_SUPPORTED (1<<12)
+
#endif /* SOC_INTEL_COMMON_MSR_H */