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-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 305748e8f3..d22cde021c 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsDevSlp));
}
+ /* Legacy 8254 timer support */
+ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+ params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
+
mainboard_silicon_init_params(params);
}