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-rw-r--r--src/mainboard/asus/a8v-e_deluxe/romstage.c1
-rw-r--r--src/mainboard/asus/a8v-e_se/romstage.c1
-rw-r--r--src/mainboard/msi/ms9282/romstage.c1
-rw-r--r--src/mainboard/msi/ms9652_fam10/romstage.c1
4 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index aab0377592..1903adc97d 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -50,7 +50,6 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index aab0377592..1903adc97d 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -50,7 +50,6 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
static void memreset(int controllers, const struct mem_controller *ctrl)
{
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index cab92767e5..6ec9daab18 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -49,7 +49,6 @@
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
#include <device/pci_ids.h>
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 36509fc556..91de477283 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -55,7 +55,6 @@
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"