diff options
72 files changed, 0 insertions, 7118 deletions
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 51c910a4d2..4871db3388 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -7,7 +7,6 @@ subdirs-$(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) += fit subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284 -subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA1023) += socket_FCBGA1023 @@ -15,7 +14,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN -subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig deleted file mode 100644 index dc19ae1c30..0000000000 --- a/src/cpu/intel/ep80579/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -config CPU_INTEL_EP80579 - bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SSE - select SUPPORT_CPU_UCODE_IN_CBFS - -if CPU_INTEL_EP80579 - -# These are just dummy values to keep build happy. -# This CPU does not have tested cache_as_ram.inc. - -config DCACHE_RAM_BASE - hex - default 0xfefc0000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - -endif diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc deleted file mode 100644 index 1af91882c4..0000000000 --- a/src/cpu/intel/ep80579/Makefile.inc +++ /dev/null @@ -1,8 +0,0 @@ -ramstage-y += ep80579.c -ramstage-y += ep80579_init.c -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode diff --git a/src/cpu/intel/ep80579/ep80579.c b/src/cpu/intel/ep80579/ep80579.c deleted file mode 100644 index 044cb4fc91..0000000000 --- a/src/cpu/intel/ep80579/ep80579.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> - -struct chip_operations cpu_intel_ep80579_ops = { - CHIP_NAME("EP80579 CPU") -}; diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c deleted file mode 100644 index d19d4e2fb7..0000000000 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/device.h> -#include <string.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/mtrr.h> - -static void ep80579_init(struct device *dev) -{ - /* Turn on caching if we haven't already */ - x86_enable_cache(); - x86_setup_mtrrs(); - x86_mtrr_check(); - - /* Update the microcode */ - intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); -}; - -static struct device_operations cpu_dev_ops = { - .init = ep80579_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x10650 }, /* EP80579 */ - { 0, 0 }, -}; - -static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig b/src/cpu/intel/socket_mPGA479M/Kconfig deleted file mode 100644 index ba6f7ea58a..0000000000 --- a/src/cpu/intel/socket_mPGA479M/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -config CPU_INTEL_SOCKET_MPGA479M - bool - select CPU_INTEL_MODEL_69X - select CPU_INTEL_MODEL_6BX - select CPU_INTEL_MODEL_6DX - select CPU_INTEL_MODEL_F2X - select MMX - select SSE - -if CPU_INTEL_SOCKET_MPGA479M - -config DCACHE_RAM_BASE - hex - default 0xc8000 - -config DCACHE_RAM_SIZE - hex - default 0x08000 - -endif diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc deleted file mode 100644 index c35ca462a0..0000000000 --- a/src/cpu/intel/socket_mPGA479M/Makefile.inc +++ /dev/null @@ -1,13 +0,0 @@ -subdirs-y += ../model_69x -subdirs-y += ../model_6dx -subdirs-y += ../model_f2x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading - -cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc -romstage-y += ../car/romstage_legacy.c diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig deleted file mode 100644 index 9671fffc7e..0000000000 --- a/src/mainboard/intel/eagleheights/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -if BOARD_INTEL_EAGLEHEIGHTS - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_BGA956 - select NORTHBRIDGE_INTEL_I3100 - select SOUTHBRIDGE_INTEL_I3100 - select SUPERIO_INTEL_I3100 - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_OPTION_TABLE - select HAVE_HARD_RESET - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 - -config MAINBOARD_DIR - string - default intel/eagleheights - -config MAINBOARD_PART_NUMBER - string - default "EagleHeights" - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - -config IRQ_SLOT_COUNT - int - default 9 - -config MAX_CPUS - int - default 4 - -endif # BOARD_INTEL_EAGLEHEIGHTS diff --git a/src/mainboard/intel/eagleheights/Kconfig.name b/src/mainboard/intel/eagleheights/Kconfig.name deleted file mode 100644 index 95be5cbc13..0000000000 --- a/src/mainboard/intel/eagleheights/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_EAGLEHEIGHTS - bool "EagleHeights" diff --git a/src/mainboard/intel/eagleheights/Makefile.inc b/src/mainboard/intel/eagleheights/Makefile.inc deleted file mode 100644 index f9621db6b3..0000000000 --- a/src/mainboard/intel/eagleheights/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-y += cstates.c diff --git a/src/mainboard/intel/eagleheights/acpi_tables.c b/src/mainboard/intel/eagleheights/acpi_tables.c deleted file mode 100644 index cd914da7f7..0000000000 --- a/src/mainboard/intel/eagleheights/acpi_tables.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/ioapic.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "ioapic.h" - -#define IO_APIC0 2 -#define IO_APIC1 3 - -unsigned long acpi_fill_madt(unsigned long current) -{ - unsigned int irq_start = 0; - device_t dev = 0; - unsigned char bus_isa; - - /* Local Apic */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0); - // This one is for the second core... Will it hurt? - current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC_ADDR, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC_ADDR + 0x10000, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; - - dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); - - if (dev) { - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - bus_isa = 7; - } - - /* Map ISA IRQ 0 to IRQ 2 */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, bus_isa, 0, 2, 0); - - /* IRQ9 differs from ISA standard - ours is active high, level-triggered */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d); - - return current; -} diff --git a/src/mainboard/intel/eagleheights/board_info.txt b/src/mainboard/intel/eagleheights/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/intel/eagleheights/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/intel/eagleheights/cmos.layout b/src/mainboard/intel/eagleheights/cmos.layout deleted file mode 100644 index eace7e704e..0000000000 --- a/src/mainboard/intel/eagleheights/cmos.layout +++ /dev/null @@ -1,96 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2007-2008 coresystems GmbH -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; version 2 of -# the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 1 e 1 power_on_after_fail -#410 6 r 0 unused - -# coreboot config options: bootloader -416 512 s 0 boot_devices -#928 80 r 0 unused - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew - -# ----------------------------------------------------------------- -checksums - -checksum 392 983 984 diff --git a/src/mainboard/intel/eagleheights/cstates.c b/src/mainboard/intel/eagleheights/cstates.c deleted file mode 100644 index f683756894..0000000000 --- a/src/mainboard/intel/eagleheights/cstates.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <arch/x86/include/arch/acpigen.h> - -int get_cst_entries(acpi_cstate_t **entries) -{ - return 0; -} diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c deleted file mode 100644 index dd97837c3f..0000000000 --- a/src/mainboard/intel/eagleheights/debug.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <spd.h> - -static void print_reg(unsigned char index) -{ - unsigned char data; - - outb(index, 0x2e); - data = inb(0x2f); - printk(BIOS_DEBUG, "0x%02x: 0x%02x\n", index, data); - return; -} - -static inline void xbus_en(void) -{ - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); - return; -} - -static void setup_func(unsigned char func) -{ - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; -} - -static inline void siodump(void) -{ - int i; - unsigned char data; - - printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n"); - for (i = 0x10; i <= 0x2d; i++) { - print_reg((unsigned char)i); - } -#if 0 - printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i = 0xf0; i <= 0xff; i++) { - print_reg((unsigned char)i); - } - - printk(BIOS_DEBUG, "\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); - - printk(BIOS_DEBUG, "\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); - -#endif - printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i = 0xf0; i <= 0xf8; i++) { - print_reg((unsigned char)i); - } - printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n"); - data = inb(0x68a); - printk(BIOS_DEBUG, "\nGPDO 4: 0x%02x", data); - data = inb(0x68b); - printk(BIOS_DEBUG, "\nGPDI 4: 0x%02x\n", data); - -#if 0 - - printk(BIOS_DEBUG, "\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); - - printk(BIOS_DEBUG, "\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); - - printk(BIOS_DEBUG, "\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); - - printk(BIOS_DEBUG, "\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); -#endif - return; -} - -static inline void dump_bar14(unsigned dev) -{ - int i; - unsigned long bar; - - printk(BIOS_DEBUG, "BAR 14 Dump\n"); - - bar = pci_read_config32(dev, 0x14); - for(i = 0; i <= 0x300; i+=4) { -#if 0 - unsigned char val; - if ((i & 0x0f) == 0) - printk(BIOS_DEBUG, "%02x:", i); - val = pci_read_config8(dev, i); -#endif - if((i%4)==0) - printk(BIOS_DEBUG, "\n%04x ", i); - printk(BIOS_DEBUG, "%08x ", read32(bar + i)); - } - printk(BIOS_DEBUG, "\n"); -} - -static inline void dump_spd_registers(void) -{ - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - printk(BIOS_DEBUG, "\ndimm %02x", device); - - for(i = 0; (i < 256); i++) { - if ((i % 16) == 0) - printk(BIOS_DEBUG, "\n%02x: ", i); - status = smbus_read_byte(device, i); - if (status < 0) { - printk(BIOS_DEBUG, "bad device: %d\n", -status); - break; - } - printk(BIOS_DEBUG, "%02x ", status); - } - device++; - printk(BIOS_DEBUG, "\n"); - } -} - -static inline void dump_ipmi_registers(void) -{ - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - printk(BIOS_DEBUG, "\nipmi %02x", device); - - for(i = 0; (i < 8); i++) { - status = smbus_read_byte(device, 2); - if (status < 0) { - printk(BIOS_DEBUG, "bad device: %d\n", -status); - break; - } - printk(BIOS_DEBUG, "%02x ", status); - } - device++; - printk(BIOS_DEBUG, "\n"); - } -} diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb deleted file mode 100644 index 8d1549af19..0000000000 --- a/src/mainboard/intel/eagleheights/devicetree.cb +++ /dev/null @@ -1,72 +0,0 @@ -chip northbridge/intel/i3100 - device domain 0 on - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x8b808a8a" - register "pirq_e_h" = "0x85808080" - - device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 off end # PCIe port B1 - device pci 1c.2 off end # PCIe port B2 - device pci 1c.3 off end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - chip superio/smsc/smscsuperio - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.2 off # Serial Port 4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 2 - end - device pnp 2e.4 off # Serial Port 3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.7 on # PS/2 Keyboard / Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.a off # Runtime registers - io 0x60 = 0x600 - end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - device pci 1f.4 on end # Performance counters - end - end - device cpu_cluster 0 on - chip cpu/intel/socket_BGA956 - device lapic 0 on end - end - end -end diff --git a/src/mainboard/intel/eagleheights/dsdt.asl b/src/mainboard/intel/eagleheights/dsdt.asl deleted file mode 100644 index 4c98e54637..0000000000 --- a/src/mainboard/intel/eagleheights/dsdt.asl +++ /dev/null @@ -1,1041 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) -{ - Scope (\_PR) - { - Processor (CPU1, 0x01, 0x00000810, 0x06) - { - OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF) - Name (NCPU, 0x80) - Name (TYPE, 0x80000000) - Name (HNDL, 0x80000000) - Name (CFGD, 0x80000000) - Name (TBLD, 0x80) - Method (_PDC, 1, NotSerialized) - { - } - } - } - - Scope (\_PR) - { - Processor (CPU2, 0x02, 0x00000000, 0x00) - { - OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF) - Name (NCPU, 0x80) - Name (TYPE, 0x80000000) - Name (HNDL, 0x80000000) - Name (CFGD, 0x80000000) - Name (TBLD, 0x80) - Method (_PDC, 1, NotSerialized) - { - } - } - } - - /* For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - * Any others would involve declaring the wake up methods. - */ - Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) - Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) - - Name (PICM, 0x00) - Method (_PIC, 1, NotSerialized) - { - Store (Arg0, PICM) - } - - /* System bus */ - Scope (\_SB) - { - /* Routing PCI0 */ - Name (PR00, Package (0x0E) - { - Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */ - Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */ - Package (0x04){0x0002FFFF,0x01,LNKB,0x00}, - Package (0x04){0x0002FFFF,0x02,LNKC,0x00}, - Package (0x04){0x0002FFFF,0x03,LNKD,0x00}, - Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */ - Package (0x04){0x0003FFFF,0x01,LNKB,0x00}, - Package (0x04){0x0003FFFF,0x02,LNKC,0x00}, - Package (0x04){0x0003FFFF,0x03,LNKD,0x00}, - Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */ - Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */ - Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */ - Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */ - Package (0x04){0x001FFFFF,0x03,LNKA,0x00} /* CHAP INTD# */ - }) - Name (AR00, Package (0x0E) - { - Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */ - Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */ - Package (0x04){0x0002FFFF,0x01,0x00,0x11}, - Package (0x04){0x0002FFFF,0x02,0x00,0x12}, - Package (0x04){0x0002FFFF,0x03,0x00,0x13}, - Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */ - Package (0x04){0x0003FFFF,0x01,0x00,0x11}, - Package (0x04){0x0003FFFF,0x02,0x00,0x12}, - Package (0x04){0x0003FFFF,0x03,0x00,0x13}, - Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */ - Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */ - Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */ - Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */ - Package (0x04){0x001FFFFF,0x0D,0x00,0x10} /* CHAP INTD# */ - }) - /* Routing PCIe Port A */ - Name (PR0A, Package (0x04) - { - Package (0x04){0xFFFF,0x00,LNKA,0x00}, - Package (0x04){0xFFFF,0x01,LNKB,0x00}, - Package (0x04){0xFFFF,0x02,LNKC,0x00}, - Package (0x04){0xFFFF,0x03,LNKD,0x00} - }) - Name (AR0A, Package (0x04) - { - Package (0x04){0xFFFF,0x00,0x00,0x10}, - Package (0x04){0xFFFF,0x01,0x00,0x11}, - Package (0x04){0xFFFF,0x02,0x00,0x12}, - Package (0x04){0xFFFF,0x03,0x00,0x13} - }) - /* Routing PCIe Port B */ - Name (PR0B, Package (0x04) - { - Package (0x04){0xFFFF,0x00,LNKA,0x00}, - Package (0x04){0xFFFF,0x01,LNKB,0x00}, - Package (0x04){0xFFFF,0x02,LNKC,0x00}, - Package (0x04){0xFFFF,0x03,LNKD,0x00} - }) - Name (AR0B, Package (0x04) - { - Package (0x04){0xFFFF,0x00,0x00,0x10}, - Package (0x04){0xFFFF,0x01,0x00,0x11}, - Package (0x04){0xFFFF,0x02,0x00,0x12}, - Package (0x04){0xFFFF,0x03,0x00,0x13} - }) - /* Routing Bus PCI */ - Name (PR01, Package (0x04) - { - Package (0x04){0x0000FFFF,0x00,LNKA,0x00}, - Package (0x04){0x0000FFFF,0x01,LNKB,0x00}, - Package (0x04){0x0000FFFF,0x02,LNKC,0x00}, - Package (0x04){0x0000FFFF,0x03,LNKD,0x00}, - }) - Name (AR01, Package (0x04) - { - Package (0x04){0x0000FFFF,0x00,0x00,0x10}, - Package (0x04){0x0000FFFF,0x01,0x00,0x11}, - Package (0x04){0x0000FFFF,0x02,0x00,0x12}, - Package (0x04){0x0000FFFF,0x03,0x00,0x13}, - }) - - Name (PRSA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,7,10,11,12,14,15} - }) - Alias (PRSA, PRSB) - Alias (PRSA, PRSC) - Alias (PRSA, PRSD) - Alias (PRSA, PRSE) - Alias (PRSA, PRSF) - Alias (PRSA, PRSG) - Alias (PRSA, PRSH) - - Device (PCI0) - { - Name (_HID, EisaId ("PNP0A08")) - Name (_CID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) - Name (_SEG, 0x00) - Name (_UID, 0x00) - Name (_BBN, 0x00) - - Name (SUPP, 0) /* PCI _OSC Support Field Value */ - Name (CTRL, 0) /* PCI _OSC Control Field Value */ - - Method (_OSC, 4) - { - /* Check for PCI/PCI-X/PCIe GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID, so set bit 2 of Arg3 to 1 */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } - } /* End _OSC */ - - Method (_PRT, 0, NotSerialized) - { - If (PICM) - { - Return (AR00) - } - - Return (PR00) - } - - /* PCI Express Port A */ - Device (EPA0) - { - Name (_ADR, 0x00020000) - Method (_PRT, 0, NotSerialized) - { - If (PICM) - { - Return (AR0A) - } - - Return (PR0A) - } - } - - /* PCI Express Port A1 */ - Device (EPA1) - { - Name (_ADR, 0x00030000) - Method (_PRT, 0, NotSerialized) - { - If (PICM) - { - Return (AR0A) - } - - Return (PR0A) - } - } - - /* PCI Express Port B0 */ - Device (EPB0) - { - Name (_ADR, 0x001C0000) - Method (_PRT, 0, NotSerialized) - { - If (PICM) - { - Return (AR0B) - } - - Return (PR0B) - } - } - - /* PCI Bridge */ - Device (P0P1) - { - Name (_ADR, 0x001E0000) - - Method (_PRT, 0, NotSerialized) - { - If (PICM) - { - Return (AR01) - } - - Return (PR01) - } - } - - /* LPC I/F Bridge */ - Device (ISA) { - Name (_ADR, 0x001F0000) - - /* MMCONF */ - Device (^PCIE) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x11) - Name (CRS, ResourceTemplate () - { - Memory32Fixed (ReadOnly, - 0xE0000000, // Address Base - 0x10000000, // Address Length - _Y10) - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1) - CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1) - Store (0xE0000000, BAS1) - Store (0x10000000, LEN1) - Return (CRS) - } - } - - /* PIC */ - Device (PIC) - { - Name (_HID, EisaId ("PNP0000")) - Name (_CRS, ResourceTemplate() - { - IO (Decode16, - 0x0020, - 0x0020, - 0x00, - 0x02, - ) - IO (Decode16, - 0x00A0, - 0x00A0, - 0x00, - 0x02, - ) - IRQNoFlags () - {2} - }) - } - - /* Real time clock */ - Device (RTC0) - { - Name (_HID, EisaId ("PNP0B00")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0070, - 0x0070, - 0x00, - 0x02) - IRQNoFlags () - {8} - }) - } - - Device (UAR1) - { - Name (_UID, 0x01) - Name (_HID, EisaId ("PNP0501")) - - Method (_PRS, 0, NotSerialized) - { - Return (CMPR) - } - - Name (CMPR, ResourceTemplate () - { - StartDependentFn (0x00, 0x00) - { - IO (Decode16,0x03F8,0x03F8,0x01,0x08) - IRQNoFlags () {4} - DMA (Compatibility, NotBusMaster, Transfer8) {} - } - StartDependentFnNoPri () - { - IO (Decode16,0x03F8,0x03F8,0x01,0x08) - IRQNoFlags () {3,4,5,6,7,10,11,12} - DMA (Compatibility, NotBusMaster, Transfer8) {} - } - StartDependentFnNoPri () - { - IO (Decode16,0x02F8,0x02F8,0x01,0x08) - IRQNoFlags () {3,4,5,6,7,10,11,12} - DMA (Compatibility, NotBusMaster, Transfer8) {} - } - StartDependentFnNoPri () - { - IO (Decode16,0x03E8,0x03E8,0x01,0x08) - IRQNoFlags () {3,4,5,6,7,10,11,12} - DMA (Compatibility, NotBusMaster, Transfer8) {} - } - StartDependentFnNoPri () - { - IO (Decode16,0x02E8,0x02E8,0x01,0x08) - IRQNoFlags () {3,4,5,6,7,10,11,12} - DMA (Compatibility, NotBusMaster, Transfer8) {} - } - EndDependentFn () - }) - } - - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} - }) - Return (TMP) - } - } - - /* COM ports of SIO */ - Device(SIO) { - Name (_ADR, 0x4E) - OperationRegion (PT4E, SystemIO, 0x4E, 0x02) - Field (PT4E, ByteAcc, NoLock, Preserve) - { - PO4E, 8, - PO4F, 8 - } - - IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve) - { - Offset (0x07), - ILDN, 8, - Offset (0x28), - SIUI, 8, - SIUC, 8, - Offset (0x30), - IACT, 8, - Offset (0x60), - IIOH, 8, - IIOL, 8, - Offset (0x70), - IINT, 8 - } - - Method (IENF, 0, NotSerialized) - { - Store (0x80, PO4E) - Store (0x86, PO4E) - } - - Method (IEXF, 0, NotSerialized) - { - Store (0x68, PO4E) - Store (0x08, PO4E) - } - - Device (COM1) - { - Name (_UID, 0x03) - Name (_HID, EisaId ("PNP0501")) - Method (_STA, 0, NotSerialized) - { - IENF () - Store (0x04, ILDN) - Store (IACT, Local0) - IEXF () - If (LEqual (Local0, 0xFF)) - { - Return (0x00) - } - - If (LEqual (Local0, One)) - { - Return (0x0F) - } - Else - { - Return (0x0D) - } - } - - Method (_DIS, 0, NotSerialized) - { - IENF () - Store (0x04, ILDN) - Store (Zero, IACT) - IEXF () - } - - Method (_CRS, 0, NotSerialized) - { - Name (BFU1, ResourceTemplate () - { - IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length - _Y03) - IRQNoFlags (_Y04) - {5} - }) - CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN) - CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX) - CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0) - IENF () - Store (0x04, ILDN) - Store (IIOH, Local0) - ShiftLeft (Local0, 0x08, Local1) - Store (IIOL, Local0) - Add (Local1, Local0, Local0) - Store (Local0, IMIN) - Store (Local0, IMAX) - Store (IINT, Local0) - IEXF () - Store (0x01, Local1) - ShiftLeft (Local1, Local0, IRQ0) - Return (BFU1) - } - - Name (_PRS, ResourceTemplate () - { - StartDependentFnNoPri () - { - IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length - ) - IRQNoFlags () - {5} - } - StartDependentFnNoPri () - { - IO (Decode16, - 0x02F8, // Range Minimum - 0x02F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length - ) - IRQNoFlags () - {9} - } - EndDependentFn () - }) - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x02, IOLO) - CreateByteField (Arg0, 0x03, IOHI) - CreateWordField (Arg0, 0x09, IRQ0) - IENF () - Store (0x04, ILDN) - Store (Zero, IACT) - Store (IOLO, IIOL) - Store (IOHI, IIOH) - FindSetRightBit (IRQ0, Local0) - If (LGreater (Local0, 0x00)) - { - Decrement (Local0) - } - - Store (Local0, IINT) - Store (One, IACT) - IEXF () - } - } /* COM1 */ - - Device (COM2) - { - Name (_UID, 0x04) - Name (_HID, EisaId ("PNP0501")) - Method (_STA, 0, NotSerialized) - { - IENF () - Store (0x05, ILDN) - Store (IACT, Local0) - IEXF () - If (LEqual (Local0, 0xFF)) - { - Return (0x00) - } - - If (LEqual (Local0, One)) - { - Return (0x0F) - } - Else - { - Return (0x0D) - } - } - - Method (_DIS, 0, NotSerialized) - { - IENF () - Store (0x05, ILDN) - Store (Zero, IACT) - IEXF () - } - - Method (_CRS, 0, NotSerialized) - { - Name (BFU1, ResourceTemplate () - { - IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length - _Y05) - IRQNoFlags (_Y06) - {9} - }) - CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN) - CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX) - CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0) - IENF () - Store (0x05, ILDN) - Store (IIOH, Local0) - ShiftLeft (Local0, 0x08, Local1) - Store (IIOL, Local0) - Add (Local1, Local0, Local0) - Store (Local0, IMIN) - Store (Local0, IMAX) - Store (IINT, Local0) - IEXF () - Store (0x01, Local1) - ShiftLeft (Local1, Local0, IRQ0) - Return (BFU1) - } - - Name (_PRS, ResourceTemplate () - { - StartDependentFnNoPri () - { - IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length - ) - IRQNoFlags () - {5} - } - StartDependentFnNoPri () - { - IO (Decode16, - 0x02F8, // Range Minimum - 0x02F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length - ) - IRQNoFlags () - {9} - } - EndDependentFn () - }) - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x02, IOLO) - CreateByteField (Arg0, 0x03, IOHI) - CreateWordField (Arg0, 0x09, IRQ0) - IENF () - Store (0x05, ILDN) - Store (Zero, IACT) - Store (IOLO, IIOL) - Store (IOHI, IIOH) - FindSetRightBit (IRQ0, Local0) - If (LGreater (Local0, 0x00)) - { - Decrement (Local0) - } - - Store (Local0, IINT) - Store (One, IACT) - IEXF () - } - } /* COM2 */ - } /* Device SIO */ - } /* Device ISA */ - } /* Device PCI 0*/ - } /* Scope SB */ - - OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C) - Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve) - { - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8, - Offset (0x08), - PIRE, 8, - PIRF, 8, - PIRG, 8, - PIRH, 8 - } - - Scope (_SB) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared, _Y1C) - {15} - }) - CreateWordField (BUFA, \_SB._Y1C._INT, IRA0) - Device (LNKA) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x01) - Method (_STA, 0, NotSerialized) - { - And (PIRA, 0x80, Local0) - If (Local0) - { - Return (0x09) - } - Else - { - Return (0x0B) - } - } - - Method (_PRS, 0, NotSerialized) - { - Return (PRSA) - } - - Method (_DIS, 0, NotSerialized) - { - Or (PIRA, 0x80, PIRA) - } - - Method (_CRS, 0, NotSerialized) - { - And (PIRA, 0x0F, Local0) - ShiftLeft (0x01, Local0, IRA0) - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateWordField (Arg0, 0x01, IRA) - FindSetRightBit (IRA, Local0) - Decrement (Local0) - Store (Local0, PIRA) - } - } - - Device (LNKB) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - And (PIRB, 0x80, Local0) - If (Local0) - { - Return (0x09) - } - Else - { - Return (0x0B) - } - } - - Method (_PRS, 0, NotSerialized) - { - Return (PRSB) - } - - Method (_DIS, 0, NotSerialized) - { - Or (PIRB, 0x80, PIRB) - } - - Method (_CRS, 0, NotSerialized) - { - And (PIRB, 0x0F, Local0) - ShiftLeft (0x01, Local0, IRA0) - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateWordField (Arg0, 0x01, IRA) - FindSetRightBit (IRA, Local0) - Decrement (Local0) - Store (Local0, PIRB) - } - } - - Device (LNKC) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x03) - Method (_STA, 0, NotSerialized) - { - And (PIRC, 0x80, Local0) - If (Local0) - { - Return (0x09) - } - Else - { - Return (0x0B) - } - } - - Method (_PRS, 0, NotSerialized) - { - Return (PRSC) - } - - Method (_DIS, 0, NotSerialized) - { - Or (PIRC, 0x80, PIRC) - } - - Method (_CRS, 0, NotSerialized) - { - And (PIRC, 0x0F, Local0) - ShiftLeft (0x01, Local0, IRA0) - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateWordField (Arg0, 0x01, IRA) - FindSetRightBit (IRA, Local0) - Decrement (Local0) - Store (Local0, PIRC) - } - } - - Device (LNKD) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x04) - Method (_STA, 0, NotSerialized) - { - And (PIRD, 0x80, Local0) - If (Local0) - { - Return (0x09) - } - Else - { - Return (0x0B) - } - } - - Method (_PRS, 0, NotSerialized) - { - Return (PRSD) - } - - Method (_DIS, 0, NotSerialized) - { - Or (PIRD, 0x80, PIRD) - } - - Method (_CRS, 0, NotSerialized) - { - And (PIRD, 0x0F, Local0) - ShiftLeft (0x01, Local0, IRA0) - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateWordField (Arg0, 0x01, IRA) - FindSetRightBit (IRA, Local0) - Decrement (Local0) - Store (Local0, PIRD) - } - } - - Device (LNKE) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x05) - Method (_STA, 0, NotSerialized) - { - And (PIRE, 0x80, Local0) - If (Local0) - { - Return (0x09) - } - Else - { - Return (0x0B) - } - } - - Method (_PRS, 0, NotSerialized) - { - Return (PRSE) - } - - Method (_DIS, 0, NotSerialized) - { - Or (PIRE, 0x80, PIRE) - } - - Method (_CRS, 0, NotSerialized) - { - And (PIRE, 0x0F, Local0) - ShiftLeft (0x01, Local0, IRA0) - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateWordField (Arg0, 0x01, IRA) - FindSetRightBit (IRA, Local0) - Decrement (Local0) - Store (Local0, PIRE) - } - } - - Device (LNKF) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x06) - Method (_STA, 0, NotSerialized) - { - And (PIRF, 0x80, Local0) - If (Local0) - { - Return (0x09) - } - Else - { - Return (0x0B) - } - } - - Method (_PRS, 0, NotSerialized) - { - Return (PRSF) - } - - Method (_DIS, 0, NotSerialized) - { - Or (PIRF, 0x80, PIRF) - } - - Method (_CRS, 0, NotSerialized) - { - And (PIRF, 0x0F, Local0) - ShiftLeft (0x01, Local0, IRA0) - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateWordField (Arg0, 0x01, IRA) - FindSetRightBit (IRA, Local0) - Decrement (Local0) - Store (Local0, PIRF) - } - } - - Device (LNKG) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x07) - Method (_STA, 0, NotSerialized) - { - And (PIRG, 0x80, Local0) - If (Local0) - { - Return (0x09) - } - Else - { - Return (0x0B) - } - } - - Method (_PRS, 0, NotSerialized) - { - Return (PRSG) - } - - Method (_DIS, 0, NotSerialized) - { - Or (PIRG, 0x80, PIRG) - } - - Method (_CRS, 0, NotSerialized) - { - And (PIRG, 0x0F, Local0) - ShiftLeft (0x01, Local0, IRA0) - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateWordField (Arg0, 0x01, IRA) - FindSetRightBit (IRA, Local0) - Decrement (Local0) - Store (Local0, PIRG) - } - } - - Device (LNKH) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x08) - Method (_STA, 0, NotSerialized) - { - And (PIRH, 0x80, Local0) - If (Local0) - { - Return (0x09) - } - Else - { - Return (0x0B) - } - } - - Method (_PRS, 0, NotSerialized) - { - Return (PRSH) - } - - Method (_DIS, 0, NotSerialized) - { - Or (PIRH, 0x80, PIRH) - } - - Method (_CRS, 0, NotSerialized) - { - And (PIRH, 0x0F, Local0) - ShiftLeft (0x01, Local0, IRA0) - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateWordField (Arg0, 0x01, IRA) - FindSetRightBit (IRA, Local0) - Decrement (Local0) - Store (Local0, PIRH) - } - } - } -} diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c deleted file mode 100644 index eaea7f71e3..0000000000 --- a/src/mainboard/intel/eagleheights/fadt.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -#define ACPI_PM1_STS (pmbase + 0x00) -#define ACPI_PM1_EN (pmbase + 0x02) -#define ACPI_PM1_CNT (pmbase + 0x04) -#define ACPI_PM1_TMR (pmbase + 0x08) -#define ACPI_PROC_CNT (pmbase + 0x10) -#define ACPI_LV2 (pmbase + 0x14) -#define ACPI_GPE0_STS (pmbase + 0x28) -#define ACPI_GPE0_EN (pmbase + 0x2C) -#define ACPI_SMI_EN (pmbase + 0x30) -#define ACPI_SMI_STS (pmbase + 0x34) -#define ACPI_ALT_GP_SMI_EN (pmbase + 0x38) -#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A) -#define ACPI_MON_SMI (pmbase + 0x40) -#define ACPI_DEVACT_STS (pmbase + 0x44) -#define ACPI_DEVTRAP_EN (pmbase + 0x48) -#define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C) -#define ACPI_BUS_CYC_TRACK (pmbase + 0x4E) - -#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS -#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT -#define ACPI_PM_TMR_BLK ACPI_PM1_TMR -#define ACPI_P_BLK ACPI_PROC_CNT -#define ACPI_GPE0_BLK ACPI_GPE0_STS - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 0; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->preferred_pm_profile = 7; /* Performance Server */ - fadt->sci_int = 0x9; -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) - fadt->smi_cmd = APM_CNT; -#else - fadt->smi_cmd = 0x00; -#endif - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = 0x0; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x28; - fadt->gpe1_blk = 0x0; - - fadt->pm1_evt_len = 0x4; - fadt->pm1_cnt_len = 0x2; - fadt->pm2_cnt_len = 0x0; - fadt->pm_tmr_len = 0x4; - fadt->gpe0_blk_len = 0x8; - fadt->gpe1_blk_len = 0x0; - fadt->gpe1_base = 0x0; - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 0x65; - fadt->p_lvl3_lat = 0x3e9; - fadt->flush_size = 0x400; - fadt->flush_stride = 0x10; - fadt->duty_offset = 0x1; - fadt->duty_width = 0x3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = 0x03; - fadt->flags = 0xa5; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - fadt->reset_value = 6; - fadt->res3 = 0; - fadt->res4 = 0; - fadt->res5 = 0; - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 32; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = 0x0; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x28; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 32; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/intel/eagleheights/ioapic.h b/src/mainboard/intel/eagleheights/ioapic.h deleted file mode 100644 index 82618f665b..0000000000 --- a/src/mainboard/intel/eagleheights/ioapic.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define IOAPIC_I3100 2 -#define INTEL_IOAPIC_NUM_INTERRUPTS 24 diff --git a/src/mainboard/intel/eagleheights/irq_tables.c b/src/mainboard/intel/eagleheights/irq_tables.c deleted file mode 100644 index 0267d62953..0000000000 --- a/src/mainboard/intel/eagleheights/irq_tables.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x2670, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x4b, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, - {0x00, (0x03 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, - {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0}, - {0x01, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x1, 0x0}, - {0x01, (0x01 << 3) | 0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c deleted file mode 100644 index dae3879be3..0000000000 --- a/src/mainboard/intel/eagleheights/mptable.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <arch/smp/mpspec.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -// Generate MP-table IRQ numbers for PCI devices. -#define IO_APIC0 2 - -#define INT_A 0 -#define INT_B 1 -#define INT_C 2 -#define INT_D 3 -#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine) - -#define PIRQ_A 16 -#define PIRQ_B 17 -#define PIRQ_C 18 -#define PIRQ_D 19 -#define PIRQ_E 20 -#define PIRQ_F 21 -#define PIRQ_G 22 -#define PIRQ_H 23 - -// RCBA -#define RCBA 0xF0 - -#define RCBA_D31IP 0x3100 -#define RCBA_D30IP 0x3104 -#define RCBA_D29IP 0x3108 -#define RCBA_D28IP 0x310C -#define RCBA_D31IR 0x3140 -#define RCBA_D30IR 0x3142 -#define RCBA_D29IR 0x3144 -#define RCBA_D28IR 0x3146 - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - unsigned char bus_chipset, bus_pci; - unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; - int bus_isa, i; - uint32_t pin, route; - device_t dev; - struct resource *res; - u8 *rcba; - - dev = dev_find_slot(0, PCI_DEVFN(0x1F,0)); - res = find_resource(dev, RCBA); - if (!res) { - return NULL; - } - rcba = res2mmio(res, 0, 0); - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - /* Get bus numbers */ - bus_chipset = 0; - - /* PCI */ - dev = dev_find_slot(0, PCI_DEVFN(0x1E,0)); - if (dev) { - bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - bus_pci = 6; - } - - dev = dev_find_slot(0, PCI_DEVFN(2,0)); - if(dev) { - bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCIe Port A 0:2.0, using defaults\n"); - bus_pcie_a = 1; - } - - dev = dev_find_slot(0, PCI_DEVFN(3,0)); - if(dev) { - bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n"); - bus_pcie_a1 = 2; - } - - dev = dev_find_slot(0, PCI_DEVFN(0x1C,0)); - if(dev) { - bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { - printk(BIOS_DEBUG, "ERROR - could not find PCIe Port B 0:3.0, using defaults\n"); - bus_pcie_b = 3; - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR); - - mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); - - /* Internal PCI device for i3100 */ - - /* EDMA - */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A); - - /* PCIe Port A - */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A); - - /* PCIe Port A1 - */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A); - - /* PCIe Port B - */ - for(i = 0; i < 4; i++) { - pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F; - if(pin > 0) { - pin -= 1; - route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route); - } - } - - /* USB 1.1 : device 29, function 0, 1 - */ - for(i = 0; i < 2; i++) { - pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F; - if(pin > 0) { - pin -= 1; - route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route); - } - } - - /* USB 2.0 : device 29, function 7 - */ - pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F; - if(pin > 0) { - pin -= 1; - route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route); - } - - /* SATA : device 31 function 2 - * SMBus : device 31 function 3 - * Performance counters : device 31 function 4 - */ - for(i = 2; i < 5; i++) { - pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F; - if(pin > 0) { - pin -= 1; - route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route); - } - } - - /* SLOTS */ - - /* PCIe 4x slot A - */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D); - - /* PCIe 4x slot A1 - */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D); - - /* PCIe 4x slot B - */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D); - - /* PCI slot - */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c deleted file mode 100644 index 21313eb491..0000000000 --- a/src/mainboard/intel/eagleheights/romstage.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include <delay.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <cpu/intel/speedstep.h> -#include "southbridge/intel/i3100/early_smbus.c" -#include "southbridge/intel/i3100/early_lpc.c" -#include "southbridge/intel/i3100/reset.c" -#include <superio/intel/i3100/i3100.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include <northbridge/intel/i3100/i3100.h> -#include <southbridge/intel/i3100/i3100.h> -#include "lib/debug.c" // XXX - -#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -#define RCBA_RPC 0x0224 /* 32 bit */ - -#define RCBA_TCTL 0x3000 /* 8 bit */ - -#define RCBA_D31IP 0x3100 /* 32 bit */ -#define RCBA_D30IP 0x3104 /* 32 bit */ -#define RCBA_D29IP 0x3108 /* 32 bit */ -#define RCBA_D28IP 0x310C /* 32 bit */ -#define RCBA_D31IR 0x3140 /* 16 bit */ -#define RCBA_D30IR 0x3142 /* 16 bit */ -#define RCBA_D29IR 0x3144 /* 16 bit */ -#define RCBA_D28IR 0x3146 /* 16 bit */ - -#define RCBA_RTC 0x3400 /* 32 bit */ -#define RCBA_HPTC 0x3404 /* 32 bit */ -#define RCBA_GCS 0x3410 /* 32 bit */ -#define RCBA_BUC 0x3414 /* 8 bit */ -#define RCBA_FD 0x3418 /* 32 bit */ -#define RCBA_PRC 0x341C /* 32 bit */ - -static inline int spd_read_byte(u16 device, u8 address) -{ - return smbus_read_byte(device, address); -} - -#include <northbridge/intel/i3100/raminit.h> -#include "northbridge/intel/i3100/memory_initialized.c" -#include "northbridge/intel/i3100/raminit.c" -#include "lib/generic_sdram.c" -#include "northbridge/intel/i3100/reset_test.c" -#include <spd.h> - -#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) - -static void early_config(void) -{ - u32 gcs, rpc, fd; - - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); - - /* Disable watchdog */ - gcs = read32(DEFAULT_RCBA + RCBA_GCS); - gcs |= (1 << 5); /* No reset */ - write32(DEFAULT_RCBA + RCBA_GCS, gcs); - - /* Configure PCIe port B as 4x */ - rpc = read32(DEFAULT_RCBA + RCBA_RPC); - rpc |= (3 << 0); - write32(DEFAULT_RCBA + RCBA_RPC, rpc); - - /* Disable Modem, Audio, PCIe ports 2/3/4 */ - fd = read32(DEFAULT_RCBA + RCBA_FD); - fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); - write32(DEFAULT_RCBA + RCBA_FD, fd); - - /* Enable HPET */ - write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); - - /* Improve interrupt routing - * D31:F2 SATA INTB# -> PIRQD - * D31:F3 SMBUS INTB# -> PIRQD - * D31:F4 CHAP INTD# -> PIRQA - * D29:F0 USB1#1 INTA# -> PIRQH - * D29:F1 USB1#2 INTB# -> PIRQD - * D29:F7 USB2 INTA# -> PIRQH - * D28:F0 PCIe Port 1 INTA# -> PIRQE - */ - - write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230); - write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210); - write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237); - write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214); - - /* Setup sata mode */ - pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); -} - -void mainboard_romstage_entry(unsigned long bist) -{ - /* int boot_mode = 0; */ - - static const struct mem_controller mch[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 }, - .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 }, - } - }; - - if (bist == 0) - enable_lapic(); - - /* Setup the console */ - i3100_enable_superio(); - i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* Perform early board specific init */ - early_config(); - - /* Prevent the TCO timer from rebooting us */ - i3100_halt_tco_timer(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - - /* Enable SpeedStep and automatic thermal throttling */ - { - msr_t msr; - u16 perf; - - msr = rdmsr(IA32_MISC_ENABLES); - msr.lo |= (1 << 3) | (1 << 16); - wrmsr(IA32_MISC_ENABLES, msr); - - /* Set CPU frequency/voltage to maximum */ - - /* Read performance status register and keep - * bits 47:32, where BUS_RATIO_MAX and VID_MAX - * are encoded - */ - msr = rdmsr(IA32_PERF_STATUS); - perf = msr.hi & 0x0000ffff; - - /* Write VID_MAX & BUS_RATIO_MAX to - * performance control register - */ - msr = rdmsr(IA32_PERF_CTL); - msr.lo &= 0xffff0000; - msr.lo |= perf; - wrmsr(IA32_PERF_CTL, msr); - } - - /* Initialize memory */ - sdram_initialize(ARRAY_SIZE(mch), mch); -} diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig deleted file mode 100644 index 11c26261c9..0000000000 --- a/src/mainboard/intel/mtarvon/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -if BOARD_INTEL_MTARVON - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_MPGA479M - select NORTHBRIDGE_INTEL_I3100 - select SOUTHBRIDGE_INTEL_I3100 - select SUPERIO_INTEL_I3100 - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select BOARD_ROMSIZE_KB_2048 - -config MAINBOARD_DIR - string - default intel/mtarvon - -config MAINBOARD_PART_NUMBER - string - default "3100 devkit (Mt. Arvon)" - -config IRQ_SLOT_COUNT - int - default 1 - -config MAX_CPUS - int - default 4 - -endif # BOARD_INTEL_MTARVON diff --git a/src/mainboard/intel/mtarvon/Kconfig.name b/src/mainboard/intel/mtarvon/Kconfig.name deleted file mode 100644 index 30b547e28f..0000000000 --- a/src/mainboard/intel/mtarvon/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_MTARVON - bool "3100 devkit (Mt. Arvon)" diff --git a/src/mainboard/intel/mtarvon/board_info.txt b/src/mainboard/intel/mtarvon/board_info.txt deleted file mode 100644 index b351b8e696..0000000000 --- a/src/mainboard/intel/mtarvon/board_info.txt +++ /dev/null @@ -1 +0,0 @@ -Category: eval diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb deleted file mode 100644 index c1ff1d585a..0000000000 --- a/src/mainboard/intel/mtarvon/devicetree.cb +++ /dev/null @@ -1,45 +0,0 @@ -chip northbridge/intel/i3100 - device domain 0 on - subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 on end # PCIe port B1 - device pci 1c.2 on end # PCIe port B2 - device pci 1c.3 on end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1e.2 on end # audio - device pci 1e.3 on end # modem - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end - device cpu_cluster 0 on - chip cpu/intel/socket_mPGA479M - device lapic 0 on end - end - end -end diff --git a/src/mainboard/intel/mtarvon/irq_tables.c b/src/mainboard/intel/mtarvon/irq_tables.c deleted file mode 100644 index 958b2d389b..0000000000 --- a/src/mainboard/intel/mtarvon/irq_tables.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ - 0x0000, /* u16 reserve IRQ for PCI */ - 0x8086, /* u16 Vendor */ - 0x2670, /* Device ID */ - 0x00000000, /* u32 miniport_data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x49, /* u8 checksum - mod 256 checksum must give zero */ - { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c deleted file mode 100644 index ee9d1c28f2..0000000000 --- a/src/mainboard/intel/mtarvon/mptable.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This code is based on src/mainboard/intel/jarrell/mptable.c */ - -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 bus_pci = 6; - u8 bus_pcie_a = 1; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - smp_write_ioapic(mc, 0x01, 0x20, VIO_APIC_VADDR); - - mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0); - - /* Standard local interrupt assignments */ - mptable_lintsrc(mc, bus_isa); - - /* Internal PCI devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x01 << 2)|0, 0x01, 0x10); /* DMA controller */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x02 << 2)|0, 0x01, 0x10); /* PCIe port A */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x03 << 2)|0, 0x01, 0x10); /* PCIe port A1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c << 2)|0, 0x01, 0x10); /* PCIe port B0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c << 2)|1, 0x01, 0x11); /* PCIe port B1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c << 2)|2, 0x01, 0x12); /* PCIe port B2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1c << 2)|3, 0x01, 0x13); /* PCIe port B3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d << 2)|0, 0x01, 0x10); /* UHCI0/EHCI */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d << 2)|1, 0x01, 0x11); /* UHCI1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1e << 2)|0, 0x01, 0x10); /* Audio */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1e << 2)|1, 0x01, 0x11); /* Modem */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f << 2)|1, 0x01, 0x11); /* SATA/SMBus */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f << 2)|3, 0x01, 0x13); /* ? */ - - /* PCI slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pci, 0x00, 0x01, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pci, 0x01, 0x01, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pci, 0x02, 0x01, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pci, 0x03, 0x01, 0x13); - - /* PCIe port A slot */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pcie_a, 0x00, 0x01, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pcie_a, 0x01, 0x01, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pcie_a, 0x02, 0x01, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - bus_pcie_a, 0x03, 0x01, 0x13); - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c deleted file mode 100644 index 13f425e1cf..0000000000 --- a/src/mainboard/intel/mtarvon/romstage.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include "southbridge/intel/i3100/early_smbus.c" -#include "southbridge/intel/i3100/early_lpc.c" -#include <northbridge/intel/i3100/raminit.h> -#include <superio/intel/i3100/i3100.h> -#include "northbridge/intel/i3100/memory_initialized.c" -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <spd.h> - -#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) -#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) - -#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) - -static inline int spd_read_byte(u16 device, u8 address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i3100/raminit.c" -#include "lib/generic_sdram.c" -#if 0 /* skip_romstage doesn't compile with gcc */ -#include "arch/x86/lib/stages.c" -#endif - -void mainboard_romstage_entry(unsigned long bist) -{ - msr_t msr; - u16 perf; - static const struct mem_controller mch[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 }, - .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 }, - } - }; - - if (bist == 0) { -#if 0 /* skip_romstage doesn't compile with gcc */ - /* Skip this if there was a built in self test failure */ - if (memory_initialized()) { - skip_romstage(); - } -#endif - } - - /* Set up the console */ - i3100_enable_superio(); - i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); - - console_init(); - - /* Prevent the TCO timer from rebooting us */ - i3100_halt_tco_timer(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - /* print_pci_devices(); */ - enable_smbus(); - /* dump_spd_registers(); */ - - /* Enable SpeedStep and automatic thermal throttling */ - /* FIXME: move to Pentium M init code */ - msr = rdmsr(0x1a0); - msr.lo |= (1 << 3) | (1 << 16); - wrmsr(0x1a0, msr); - msr = rdmsr(0x19d); - msr.lo |= (1 << 16); - wrmsr(0x19d, msr); - - /* Set CPU frequency/voltage to maximum */ - /* FIXME: move to Pentium M init code */ - msr = rdmsr(IA32_PERF_STATUS); - perf = msr.hi & 0xffff; - msr = rdmsr(0x199); - msr.lo &= 0xffff0000; - msr.lo |= perf; - wrmsr(0x199, msr); - - sdram_initialize(ARRAY_SIZE(mch), mch); - /* dump_pci_devices(); */ - /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */ - /* dump_bar14(PCI_DEV(0, 0x00, 0)); */ -} diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig deleted file mode 100644 index cd8e478f1b..0000000000 --- a/src/mainboard/intel/truxton/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -if BOARD_INTEL_TRUXTON - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_EP80579 - select NORTHBRIDGE_INTEL_I3100 - select SOUTHBRIDGE_INTEL_I3100 - select SUPERIO_INTEL_I3100 - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_HARD_RESET - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select BOARD_ROMSIZE_KB_2048 - -config MAINBOARD_DIR - string - default intel/truxton - -config MAINBOARD_PART_NUMBER - string - default "Truxton" - -config IRQ_SLOT_COUNT - int - default 1 - -config MAX_CPUS - int - default 4 - -endif # BOARD_INTEL_TRUXTON diff --git a/src/mainboard/intel/truxton/Kconfig.name b/src/mainboard/intel/truxton/Kconfig.name deleted file mode 100644 index f91b44538f..0000000000 --- a/src/mainboard/intel/truxton/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_TRUXTON - bool "EP80579 devkit (Truxton)" diff --git a/src/mainboard/intel/truxton/Makefile.inc b/src/mainboard/intel/truxton/Makefile.inc deleted file mode 100644 index 6ef4fc9d50..0000000000 --- a/src/mainboard/intel/truxton/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 diff --git a/src/mainboard/intel/truxton/board_info.txt b/src/mainboard/intel/truxton/board_info.txt deleted file mode 100644 index 5ae0fde757..0000000000 --- a/src/mainboard/intel/truxton/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Board name: EP80579 devkit (Truxton) -Category: eval -Release year: 2009 diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb deleted file mode 100644 index 05fb05ecf1..0000000000 --- a/src/mainboard/intel/truxton/devicetree.cb +++ /dev/null @@ -1,55 +0,0 @@ -chip northbridge/intel/i3100 - device domain 0 on - subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - device pci 04.0 on end # ? - device pci 08.0 off end # must be off to boot - device pci 0d.0 off end # must be off to boot - device pci 0d.1 off end # must be off to boot - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1d.0 on end # USB (UHCI) - device pci 1d.7 on end # USB (EHCI) - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - chip superio/smsc/smscsuperio - device pnp 2e.0 off end - device pnp 2e.3 off end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.a off end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - device pci 1f.4 on end # ? - end - end - device cpu_cluster 0 on - chip cpu/intel/ep80579 - device lapic 0 on end - end - end -end diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c deleted file mode 100644 index c34809f677..0000000000 --- a/src/mainboard/intel/truxton/irq_tables.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ - 0x0000, /* u16 reserve IRQ for PCI */ - 0x8086, /* u16 Vendor */ - 0x5031, /* Device ID */ - 0x00000000, /* u32 miniport_data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5e, /* u8 checksum - mod 256 checksum must give zero */ - { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c deleted file mode 100644 index ca934b3aee..0000000000 --- a/src/mainboard/intel/truxton/mptable.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 bus_pea0 = 0; - u8 bus_pea1 = 0; - u8 bus_aioc; - device_t dev; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - /* AIOC bridge */ - dev = dev_find_slot(0, PCI_DEVFN(0x04,0)); - if (dev) { - bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n"); - bus_aioc = 0; - } - /* PCIe A0 */ - dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n"); - bus_pea0 = 0; - } - /* PCIe A1 */ - dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n"); - bus_pea1 = 0; - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - smp_write_ioapic(mc, 0x8, 0x20, VIO_APIC_VADDR); - - mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0); - - /* Standard local interrupt assignments */ - mptable_lintsrc(mc, bus_isa); - - /* IMCH/IICH PCI devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x01 << 2)|0, 0x8, 0x10); /* DMA controller */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x02 << 2)|0, 0x8, 0x10); /* PCIe port A bridge */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x03 << 2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x04 << 2)|0, 0x8, 0x10); /* AIOC PCI bridge */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d << 2)|0, 0x8, 0x10); /* UHCI/EHCI */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f << 2)|1, 0x8, 0x11); /* SATA/SMBus */ - - if (bus_pea0) { - /* PCIe slot 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0 << 2)|0, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0 << 2)|1, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0 << 2)|2, 0x8, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0 << 2)|3, 0x8, 0x13); - } - - if (bus_pea1) { - /* PCIe slots 1-4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0 << 2)|0, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0 << 2)|1, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0 << 2)|2, 0x8, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0 << 2)|3, 0x8, 0x13); - } - - if (bus_aioc) { - /* AIOC PCI devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (0 << 2)|0, 0x8, 0x10); /* GbE0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (1 << 2)|0, 0x8, 0x11); /* GbE1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (2 << 2)|0, 0x8, 0x12); /* GbE2 */ - } - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c deleted file mode 100644 index 4b64210c38..0000000000 --- a/src/mainboard/intel/truxton/romstage.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include "southbridge/intel/i3100/early_smbus.c" -#include "southbridge/intel/i3100/early_lpc.c" -#include <northbridge/intel/i3100/raminit_ep80579.h> -#include <superio/intel/i3100/i3100.h> -#include "lib/debug.c" // XXX -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <spd.h> - -#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) - -static inline int spd_read_byte(u16 device, u8 address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i3100/raminit_ep80579.c" -#include "lib/generic_sdram.c" - -#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - static const struct mem_controller mch[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x00, 0), - .channel0 = { DIMM2, DIMM3 }, - } - }; - - if (bist == 0) { - /* Skip this if there was a built in self test failure */ - if (memory_initialized()) - return; - } - - /* Set up the console */ - i3100_enable_superio(); - i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); - - console_init(); - - /* Prevent the TCO timer from rebooting us */ - i3100_halt_tco_timer(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - -#ifdef TRUXTON_DEBUG - print_pci_devices(); -#endif - enable_smbus(); - - sdram_initialize(ARRAY_SIZE(mch), mch); - dump_pci_devices(); - dump_pci_device(PCI_DEV(0, 0x00, 0)); -#ifdef TRUXTON_DEBUG - dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif -} diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig deleted file mode 100644 index a7c4a1daab..0000000000 --- a/src/northbridge/intel/i3100/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -config NORTHBRIDGE_INTEL_I3100 - bool - select NO_MMCONF_SUPPORT - select LATE_CBMEM_INIT - -if NORTHBRIDGE_INTEL_I3100 -config DIMM_MAP_LOGICAL - hex - default 0x1248 - -endif diff --git a/src/northbridge/intel/i3100/Makefile.inc b/src/northbridge/intel/i3100/Makefile.inc deleted file mode 100644 index 16291bf5d8..0000000000 --- a/src/northbridge/intel/i3100/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I3100),y) - -ramstage-y += northbridge.c -ramstage-y += pciexp_porta.c -ramstage-y += pciexp_porta_ep80579.c - -endif diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h deleted file mode 100644 index 5da74318ce..0000000000 --- a/src/northbridge/intel/i3100/chip.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I3100_CHIP_H -#define NORTHBRIDGE_INTEL_I3100_CHIP_H - -struct northbridge_intel_i3100_config -{ - /* Interrupt line connect */ - u16 intrline; -}; - -#endif /* NORTHBRIDGE_INTEL_I3100_CHIP_H */ diff --git a/src/northbridge/intel/i3100/ep80579.h b/src/northbridge/intel/i3100/ep80579.h deleted file mode 100644 index 60c319f593..0000000000 --- a/src/northbridge/intel/i3100/ep80579.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I3100_EP80579_H -#define NORTHBRIDGE_INTEL_I3100_EP80579_H - -#define SMRBASE 0x14 -#define MCHCFG0 0x50 -#define FDHC 0x58 -#define PAM 0x59 -#define DRB 0x60 -#define DRT1 0x64 -#define DRA 0x70 -#define DRT0 0x78 -#define DRC 0x7c -#define ECCDIAG 0x84 -#define SDRC 0x88 -#define CKDIS 0x8c -#define CKEDIS 0x8d -#define DEVPRES 0x9c -#define DEVPRES_D0F0 (1 << 0) -#define DEVPRES_D1F0 (1 << 1) -#define DEVPRES_D2F0 (1 << 2) -#define DEVPRES_D3F0 (1 << 3) -#define DEVPRES_D4F0 (1 << 4) -#define DEVPRES_D10F0 (1 << 5) -#define EXSMRC 0x9d -#define SMRAM 0x9e -#define EXSMRAMC 0x9f -#define DDR2ODTC 0xb0 -#define TOLM 0xc4 -#define REMAPBASE 0xc6 -#define REMAPLIMIT 0xc8 -#define REMAPOFFSET 0xca -#define TOM 0xcc -#define HECBASE 0xce -#define DEVPRES1 0xf4 - -#define DCALCSR 0x040 -#define DCALADDR 0x044 -#define DCALDATA 0x048 -#define MBCSR 0x140 -#define MBADDR 0x144 -#define MBDATA 0x148 -#define DDRIOMC2 0x268 - -#endif diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h deleted file mode 100644 index b501e0b88a..0000000000 --- a/src/northbridge/intel/i3100/i3100.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __I3100_H__ -#define __I3100_H__ - -#define IURBASE 0X14 -#define MCHCFG0 0X50 -#define MCHSCRB 0X52 -#define FDHC 0X58 -#define PAM 0X59 -#define DRB 0X60 -#define DRA 0X70 -#define DRT 0X78 -#define DRC 0X7C -#define DRM 0X80 -#define DRORC 0X82 -#define ECCDIAG 0X84 -#define SDRC 0X88 -#define CKDIS 0X8C -#define CKEDIS 0X8D -#define DDRCSR 0X9A -#define DEVPRES 0X9C -#define DEVPRES_D0F0 (1 << 0) -#define DEVPRES_D1F0 (1 << 1) -#define DEVPRES_D2F0 (1 << 2) -#define DEVPRES_D3F0 (1 << 3) -#define DEVPRES_D4F0 (1 << 4) -#define DEVPRES_D5F0 (1 << 5) -#define DEVPRES_D6F0 (1 << 6) -#define DEVPRES_D7F0 (1 << 7) -#define ESMRC 0X9D -#define SMRC 0X9E -#define EXSMRC 0X9F -#define DDR2ODTC 0XB0 -#define TOLM 0XC4 -#define REMAPBASE 0XC6 -#define REMAPLIMIT 0XC8 -#define REMAPOFFSET 0XCA -#define TOM 0XCC -#define EXPECBASE 0XCE -#define DEVPRES1 0XF4 -#define DEVPRES1_D0F1 (1 << 5) -#define DEVPRES1_D8F0 (1 << 1) -#define MSCFG 0XF6 - -/* DRC */ -#define DRC_NOECC_MODE (0 << 20) -#define DRC_72BIT_ECC (1 << 20) - -#define RCBA 0xF0 -#define DEFAULT_RCBA ((u8 *)0xFEA00000) - -int bios_reset_detected(void); - -#endif diff --git a/src/northbridge/intel/i3100/memory_initialized.c b/src/northbridge/intel/i3100/memory_initialized.c deleted file mode 100644 index 6af7b9bca8..0000000000 --- a/src/northbridge/intel/i3100/memory_initialized.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "i3100.h" -#define NB_DEV PCI_DEV(0, 0, 0) - -static inline int memory_initialized(void) -{ - u32 drc; - drc = pci_read_config32(NB_DEV, DRC); - return (drc & (1<<29)); -} diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c deleted file mode 100644 index f05eea0464..0000000000 --- a/src/northbridge/intel/i3100/northbridge.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/e7520/northbridge.c */ - -#include <console/console.h> -#include <arch/io.h> -#include <stdint.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> -#include <string.h> -#include <cbmem.h> -#include <cpu/cpu.h> -#include "chip.h" -#include "i3100.h" -#include <arch/acpi.h> - - -static void pci_domain_set_resources(device_t dev) -{ - device_t mc_dev; - u32 pci_tolm; - - pci_tolm = find_pci_tolm(dev->link_list); - -#if 1 - printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); -#endif - /* FIXME Me temporary hack */ - if (pci_tolm > 0xe0000000) - pci_tolm = 0xe0000000; - /* Ensure pci_tolm is 128M aligned */ - pci_tolm &= 0xf8000000; - mc_dev = dev->link_list->children; - if (mc_dev) { - /* Figure out which areas are/should be occupied by RAM. - * This is all computed in kilobytes and converted to/from - * the memory controller right at the edges. - * Having different variables in different units is - * too confusing to get right. Kilobytes are good up to - * 4 Terabytes of RAM... - */ - u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r; - u32 tomk, tolmk; - u32 remapbasek, remaplimitk, remapoffsetk; - - /* Get the Top of Memory address, units are 128M */ - tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17; - /* Compute the Top of Low Memory */ - tolmk = (pci_tolm & 0xf8000000) >> 10; - - if (tolmk >= tomk) { - /* The PCI hole does not overlap memory - * we won't use the remap window. - */ - tolmk = tomk; - remapbasek = 0x3ff << 16; - remaplimitk = 0 << 16; - remapoffsetk = 0 << 16; - } - else { - /* The PCI memory hole overlaps memory - * setup the remap window. - */ - /* Find the bottom of the remap window - * is it above 4G? - */ - remapbasek = 4*1024*1024; - if (tomk > remapbasek) { - remapbasek = tomk; - } - /* Find the limit of the remap window */ - remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); - /* Find the offset of the remap window from tolm */ - remapoffsetk = remapbasek - tolmk; - } - /* Write the RAM configuration registers, - * preserving the reserved bits. - */ - tolm_r = pci_read_config16(mc_dev, 0xc4); - tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff); - pci_write_config16(mc_dev, 0xc4, tolm_r); - - remapbase_r = pci_read_config16(mc_dev, 0xc6); - remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); - pci_write_config16(mc_dev, 0xc6, remapbase_r); - - remaplimit_r = pci_read_config16(mc_dev, 0xc8); - remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); - pci_write_config16(mc_dev, 0xc8, remaplimit_r); - - remapoffset_r = pci_read_config16(mc_dev, 0xca); - remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00); - pci_write_config16(mc_dev, 0xca, remapoffset_r); - - /* Report the memory regions */ - ram_resource(dev, 3, 0, 640); - ram_resource(dev, 4, 768, (tolmk - 768)); - if (tomk > 4*1024*1024) { - ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024); - } - if (remaplimitk >= remapbasek) { - ram_resource(dev, 6, remapbasek, - (remaplimitk + 64*1024) - remapbasek); - } - - set_late_cbmem_top(tolmk * 1024); - } - assign_resources(dev->link_list); -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; - -static void mc_read_resources(device_t dev) -{ - pci_dev_read_resources(dev); - - mmconf_resource(dev, EXPECBASE); -} - -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - device_t dev; - u64 mmcfg; - - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 - if (!dev) - return current; - - // MMCFG not supported or not enabled. - mmcfg = ((u64) pci_read_config16(dev, 0xce)) << 16; - if (!mmcfg) - return current; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - mmcfg, 0x0, 0x0, 0xff); - - return current; -} - -#endif - -static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, -}; - -static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, -}; - -static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_MC, -}; - -static void cpu_bus_init(device_t dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - - -static void enable_dev(device_t dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_i3100_ops = { - CHIP_NAME("Intel 3100 Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c deleted file mode 100644 index 3f4939cace..0000000000 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pciexp.h> -#include <arch/io.h> -#include "chip.h" -#include <reset.h> - -typedef struct northbridge_intel_i3100_config config_t; - -static void pcie_init(struct device *dev) -{ - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if (config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } - -} - -static void pcie_scan_bridge(struct device *dev) -{ - u16 val; - u16 ctl; - int flag = 0; - do { - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); - if ((val & (1<<10)) && (!flag)) { /* training error */ - ctl = pci_read_config16(dev, 0x74); - pci_write_config16(dev, 0x74, (ctl | (1<<5))); - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); - flag = 1; - hard_reset(); - } - } while (val & (3<<10)); - - pciexp_scan_bridge(dev); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA0, -}; - -static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA1, -}; diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c deleted file mode 100644 index 62f485d705..0000000000 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 4DSP Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/i3100/pciexp_porta.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pciexp.h> -#include <arch/io.h> -#include "chip.h" -#include <reset.h> - -typedef struct northbridge_intel_i3100_config config_t; - -static void pcie_init(struct device *dev) -{ - config_t *config; - u16 val; - - /* Get the chip configuration */ - config = dev->chip_info; - - if (config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } - - printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n"); - val = pci_read_config16(dev, 0x66); - val &= ~(1<<8); - val |= 1<<8; - pci_write_config16(dev, 0x66, val); - - /* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */ -} - - -static void pcie_bus_enable_resources(struct device *dev) -{ - if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); - pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); - - dev->command |= PCI_COMMAND_IO; - dev->command |= PCI_COMMAND_MEMORY; - } - pci_dev_enable_resources(dev); -} - - -static void pcie_scan_bridge(struct device *dev) -{ - u16 val; - u16 ctl; - int flag = 0; - do { - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); - if ((val & (1<<11)) && (!flag)) { /* training error */ - ctl = pci_read_config16(dev, 0x74); - pci_write_config16(dev, 0x74, (ctl | (1<<5))); - val = pci_read_config16(dev, 0x76); - printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); - flag = 1; - hard_reset(); - } - } while (val & (3<<10)); - - pciexp_scan_bridge(dev); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pcie_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0, -}; - -static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1, -}; diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c deleted file mode 100644 index aebe4e864b..0000000000 --- a/src/northbridge/intel/i3100/raminit.c +++ /dev/null @@ -1,1201 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/intel/speedstep.h> -#include <lib.h> -#include <stdlib.h> -#include "raminit.h" -#include "i3100.h" - -/* DDR2 memory controller register space */ -#define MCBAR ((u8 *)(0x90000000)) - -static void sdram_set_registers(const struct mem_controller *ctrl) -{ - static const u32 register_values[] = { - - /* CKDIS 0x8c disable clocks */ - PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - - /* 0x9c Device present and extended RAM control - * DEVPRES is very touchy, hard code the initialization - * of PCI-E ports here. - */ - PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, - - /* 0xc8 Remap RAM base and limit off */ - PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, - - /* ??? */ - PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000, - PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a, - - /* 0x50 scrub */ - PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */ - - /* 0x58 0x5c PAM */ - PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, - PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, - - /* 0xf4 */ - PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, - - /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0), - }; - int i; - int max; - - max = ARRAY_SIZE(register_values); - for (i = 0; i < max; i += 3) { - device_t dev; - u32 where; - u32 reg; - dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } - printk(BIOS_SPEW, "done.\n"); -} - -struct dimm_size { - u32 side1; - u32 side2; -}; - -static struct dimm_size spd_get_dimm_size(u16 device) -{ - /* Calculate the log base 2 size of a DIMM in bits */ - struct dimm_size sz; - int value, low; - sz.side1 = 0; - sz.side2 = 0; - - /* Note it might be easier to use byte 31 here, it has the DIMM size as - * a multiple of 4MB. The way we do it now we can size both - * sides of an asymmetric dimm. - */ - value = spd_read_byte(device, 3); /* rows */ - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - sz.side1 += value & 0xf; - - value = spd_read_byte(device, 4); /* columns */ - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - sz.side1 += value & 0xf; - - value = spd_read_byte(device, 17); /* banks */ - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side1 += log2(value & 0xff); - - /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, 7); /* (high byte) */ - if (value < 0) goto hw_err; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, 6); /* (low byte) */ - if (low < 0) goto hw_err; - value = value | (low & 0xff); - if ((value != 72) && (value != 64)) goto val_err; - sz.side1 += log2(value); - - /* side 2 */ - value = spd_read_byte(device, 5); /* number of physical banks */ - - if (value < 0) goto hw_err; - value &= 7; - value++; - if (value == 1) goto out; - if (value != 2) goto val_err; - - /* Start with the symmetrical case */ - sz.side2 = sz.side1; - - value = spd_read_byte(device, 3); /* rows */ - if (value < 0) goto hw_err; - if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */ - sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */ - sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */ - - value = spd_read_byte(device, 4); /* columns */ - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */ - sz.side2 += ((value >> 4) & 0x0f); /* Add in columns on side 2 */ - goto out; - - val_err: - die("Bad SPD value\n"); - /* If an hw_error occurs report that I have no memory */ - hw_err: - sz.side1 = 0; - sz.side2 = 0; -out: - return sz; - -} - -static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) -{ - int i; - int cum; - - for (i = cum = 0; i < DIMM_SOCKETS; i++) { - struct dimm_size sz; - if (dimm_mask & (1 << i)) { - sz = spd_get_dimm_size(ctrl->channel0[i]); - if (sz.side1 < 29) { - return -1; /* Report SPD error */ - } - /* convert bits to multiples of 64MB */ - sz.side1 -= 29; - cum += (1 << sz.side1); - /* DRB = 0x60 */ - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - if ( sz.side2 > 28) { - sz.side2 -= 29; - cum += (1 << sz.side2); - } - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); - } - else { - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); - } - } - cum >>= 1; - /* set TOM top of memory 0xcc */ - pci_write_config16(ctrl->f0, TOM, cum); - /* set TOLM top of low memory */ - if (cum > 0x18) { - cum = 0x18; - } - cum <<= 11; - /* 0xc4 TOLM */ - pci_write_config16(ctrl->f0, TOLM, cum); - return 0; -} - - -static u32 spd_detect_dimms(const struct mem_controller *ctrl) -{ - u32 dimm_mask; - int i; - dimm_mask = 0; - for (i = 0; i < DIMM_SOCKETS; i++) { - int byte; - u16 device; - device = ctrl->channel0[i]; - if (device) { - byte = spd_read_byte(device, 2); /* Type */ - if (byte == 8) { - dimm_mask |= (1 << i); - } - } - device = ctrl->channel1[i]; - if (device) { - byte = spd_read_byte(device, 2); - if (byte == 8) { - dimm_mask |= (1 << (i + DIMM_SOCKETS)); - } - } - } - return dimm_mask; -} - - -static int spd_set_row_attributes(const struct mem_controller *ctrl, - long dimm_mask) -{ - int value; - int reg; - int dra; - int cnt; - - dra = 0; - for (cnt = 0; cnt < 4; cnt++) { - if (!(dimm_mask & (1 << cnt))) { - continue; - } - reg =0; - value = spd_read_byte(ctrl->channel0[cnt], 3); /* rows */ - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - reg += value & 0xf; - - value = spd_read_byte(ctrl->channel0[cnt], 4); /* columns */ - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - reg += value & 0xf; - - value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */ - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - reg += log2(value & 0xff); - - /* Get the device width and convert it to a power of two */ - value = spd_read_byte(ctrl->channel0[cnt], 13); - if (value < 0) goto hw_err; - value = log2(value & 0xff); - reg += value; - if (reg < 27) goto hw_err; - reg -= 27; - reg += (value << 2); - - dra += reg << (cnt*8); - value = spd_read_byte(ctrl->channel0[cnt], 5); - if (value & 2) - dra += reg << ((cnt*8)+4); - } - - /* 0x70 DRA */ - pci_write_config32(ctrl->f0, DRA, dra); - goto out; - - val_err: - die("Bad SPD value\n"); - /* If an hw_error occurs report that I have no memory */ - hw_err: - dra = 0; -out: - return dra; - -} - - -static int spd_set_drt_attributes(const struct mem_controller *ctrl, - long dimm_mask, u32 drc) -{ - int value; - int reg; - u32 drt; - int cnt; - int first_dimm; - int cas_latency = 0; - int latency; - u32 index = 0; - u32 index2 = 0; - static const u8 cycle_time[3] = { 0x75, 0x60, 0x50 }; - static const u8 latency_indicies[] = { 26, 23, 9 }; - - /* 0x78 DRT */ - drt = pci_read_config32(ctrl->f0, DRT); - drt &= 3; /* save bits 1:0 */ - - for (first_dimm = 0; first_dimm < 4; first_dimm++) { - if (dimm_mask & (1 << first_dimm)) - break; - } - - drt |= (1<<6); /* back to back write turn around */ - - drt |= (3<<18); /* Trasmax */ - - for (cnt = 0; cnt < 4; cnt++) { - if (!(dimm_mask & (1 << cnt))) { - continue; - } - reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */ - /* Compute the lowest cas latency supported */ - latency = log2(reg) -2; - - /* Loop through and find a fast clock with a low latency */ - for (index = 0; index < 3; index++, latency++) { - if ((latency < 2) || (latency > 4) || - (!(reg & (1 << latency)))) { - continue; - } - value = spd_read_byte(ctrl->channel0[cnt], - latency_indicies[index]); - - if (value <= cycle_time[drc & 3]) { - if ( latency > cas_latency) { - cas_latency = latency; - } - break; - } - } - } - index = (cas_latency-2); - if ((index) == 0) cas_latency = 20; - else if ((index) == 1) cas_latency = 25; - else cas_latency = 30; - - for (cnt = 0; cnt < 4; cnt++) { - if (!(dimm_mask & (1 << cnt))) { - continue; - } - reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff; - if (((index>>8) & 0x0ff) < reg) { - index &= ~(0x0ff << 8); - index |= (reg << 8); - } - reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff; - if (((index>>16) & 0x0ff) < reg) { - index &= ~(0x0ff << 16); - index |= (reg<<16); - } - reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff; - if (((index2>>0) & 0x0ff) < reg) { - index2 &= ~(0x0ff << 0); - index2 |= (reg<<0); - } - reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff; - if (((index2>>8) & 0x0ff) < reg) { - index2 &= ~(0x0ff << 8); - index2 |= (reg<<8); - } - reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff; - if (((index2>>16) & 0x0ff) < reg) { - index2 &= ~(0x0ff << 16); - index2 |= (reg<<16); - } - } - - /* get dimm speed */ - value = cycle_time[drc & 3]; - if (value <= 0x50) { /* 200 MHz */ - if ((index & 7) > 2) { - drt |= (2<<2); /* CAS latency 4 */ - cas_latency = 40; - } else { - drt |= (1<<2); /* CAS latency 3 */ - cas_latency = 30; - } - if ((index & 0x0ff00) <= 0x03c00) { - drt |= (1<<8); /* Trp RAS Precharge */ - } else { - drt |= (2<<8); /* Trp RAS Precharge */ - } - - /* Trcd RAS to CAS delay */ - if ((index2 & 0x0ff) <= 0x03c) { - drt |= (0<<10); - } else { - drt |= (1<<10); - } - - /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - - /* Trc TRS min */ - if ((index2 & 0x0ff00) <= 0x03700) - drt |= (0<<14); - else if ((index2 & 0xff00) <= 0x03c00) - drt |= (1<<14); - else - drt |= (2<<14); /* spd 41 */ - - drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ - - /* Trrd Row Delay */ - if ((index & 0x0ff0000) <= 0x0140000) { - drt |= (0<<20); - } else if ((index & 0x0ff0000) <= 0x0280000) { - drt |= (1<<20); - } else if ((index & 0x0ff0000) <= 0x03c0000) { - drt |= (2<<20); - } else { - drt |= (3<<20); - } - - /* Trfc Auto refresh cycle time */ - if ((index2 & 0x0ff0000) <= 0x04b0000) { - drt |= (0<<22); - } else if ((index2 & 0x0ff0000) <= 0x0690000) { - drt |= (1<<22); - } else { - drt |= (2<<22); - } - /* Docs say use 55 for all 200MHz */ - drt |= (0x055<<24); - } - else if (value <= 0x60) { /* 167 MHz */ - /* according to new documentation CAS latency is 00 - * for bits 3:2 for all 167 MHz - drt |= ((index & 3)<<2); */ /* set CAS latency */ - if ((index & 0x0ff00) <= 0x03000) { - drt |= (1<<8); /* Trp RAS Precharge */ - } else { - drt |= (2<<8); /* Trp RAS Precharge */ - } - - /* Trcd RAS to CAS delay */ - if ((index2 & 0x0ff) <= 0x030) { - drt |= (0<<10); - } else { - drt |= (1<<10); - } - - /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); - - /* Trc TRS min */ - drt |= (2<<14); /* spd 41, but only one choice */ - - drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ - - /* Trrd Row Delay */ - if ((index & 0x0ff0000) <= 0x0180000) { - drt |= (0<<20); - } else if ((index & 0x0ff0000) <= 0x0300000) { - drt |= (1<<20); - } else { - drt |= (2<<20); - } - - /* Trfc Auto refresh cycle time */ - if ((index2 & 0x0ff0000) <= 0x0480000) { - drt |= (0<<22); - } else if ((index2 & 0x0ff0000) <= 0x0780000) { - drt |= (2<<22); - } else { - drt |= (2<<22); - } - /* Docs state to use 99 for all 167 MHz */ - drt |= (0x099<<24); - } - else if (value <= 0x75) { /* 133 MHz */ - drt |= ((index & 3)<<2); /* set CAS latency */ - if ((index & 0x0ff00) <= 0x03c00) { - drt |= (1<<8); /* Trp RAS Precharge */ - } else { - drt |= (2<<8); /* Trp RAS Precharge */ - } - - /* Trcd RAS to CAS delay */ - if ((index2 & 0x0ff) <= 0x03c) { - drt |= (0<<10); - } else { - drt |= (1<<10); - } - - /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - - /* Trc TRS min */ - drt |= (2<<14); /* spd 41, but only one choice */ - - drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ - - /* Trrd Row Delay */ - if ((index & 0x0ff0000) <= 0x01e0000) { - drt |= (0<<20); - } else if ((index & 0x0ff0000) <= 0x03c0000) { - drt |= (1<<20); - } else { - drt |= (2<<20); - } - - /* Trfc Auto refresh cycle time */ - if ((index2 & 0x0ff0000) <= 0x04b0000) { - drt |= (0<<22); - } else if ((index2 & 0x0ff0000) <= 0x0780000) { - drt |= (2<<22); - } else { - drt |= (2<<22); - } - - /* Based on CAS latency */ - if (index & 7) - drt |= (0x099<<24); - else - drt |= (0x055<<24); - - } - else { - die("Invalid SPD 9 bus speed.\n"); - } - - /* 0x78 DRT */ - pci_write_config32(ctrl->f0, DRT, drt); - - return(cas_latency); -} - -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, - long dimm_mask) -{ - int value; - int drc; - int cnt; - msr_t msr; - u8 rate = 62; - static const u8 spd_rates[6] = {15,3,7,7,62,62}; - static const u8 drc_rates[5] = {0,15,7,62,3}; - static const u8 fsb_conversion[8] = {0,1,3,2,3,0,3,3}; - - /* 0x7c DRC */ - drc = pci_read_config32(ctrl->f0, DRC); - for (cnt = 0; cnt < 4; cnt++) { - if (!(dimm_mask & (1 << cnt))) { - continue; - } - value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */ - if (value != 2) die("ERROR - Non ECC memory dimm\n"); - - value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/ - value &= 0x0f; /* clip self refresh bit */ - if (value > 5) goto hw_err; - if (rate > spd_rates[value]) - rate = spd_rates[value]; - - value = spd_read_byte(ctrl->channel0[cnt], 9); /* cycle time */ - if (value > 0x75) goto hw_err; - } - drc |= (1 << 20); /* enable ECC */ - for (cnt = 1; cnt < 5; cnt++) - if (drc_rates[cnt] == rate) - break; - if (cnt < 5) { - drc &= ~(7 << 8); /* clear the rate bits */ - drc |= (cnt << 8); - } - - drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */ - drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */ - drc |= (1 << 7); - drc &= ~(1 << 5); /* enable ODT */ - drc |= (1 << 4); /* independent clocks */ - - /* set front side bus speed */ - msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ - value = msr.lo & 0x07; - drc &= ~(3 << 2); - drc |= (fsb_conversion[value] << 2); - - /* set dram type to ddr2 */ - drc &= ~(3 << 0); - drc |= (2 << 0); - - goto out; - - /* If an hw_error occurs report that I have no memory */ - hw_err: - drc = 0; -out: - return drc; -} - -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - long dimm_mask; - - /* Test if we can read the spd and if RAM is ddr or ddr2 */ - dimm_mask = spd_detect_dimms(ctrl); - if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - printk(BIOS_ERR, "No memory for this cpu\n"); - return; - } - return; -} - -static void do_delay(void) -{ - int i; - u8 b; - for (i = 0; i < 16; i++) - b = inb(0x80); -} - -#define TIMEOUT_LOOPS 300000 - -#define DCALCSR 0x100 -#define DCALADDR 0x104 -#define DCALDATA 0x108 - -static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) -{ - u8 c1,c2; - u32 dimm,i; - u32 data32 = 0; - u32 t4; - - /* Set up northbridge values */ - /* ODT enable */ - pci_write_config32(ctrl->f0, SDRC, 0x30000000); - /* Figure out which slots are Empty, Single, or Double sided */ - for (i = 0,t4 = 0,c2 = 0; i < 8; i+=2) { - c1 = pci_read_config8(ctrl->f0, DRB+i); - if (c1 == c2) continue; - c2 = pci_read_config8(ctrl->f0, DRB+1+i); - if (c1 == c2) - t4 |= (1 << (i*4)); - else - t4 |= (2 << (i*4)); - } - for (i = 0; i < 1; i++) { - if ((t4 & 0x0f) == 1) { - if ( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00000010; /* EEES */ - break; - } - if ( ((t4>>16)&0x0f) == 0 ) { - data32 = 0x00003132; /* EESS */ - break; - } - if ( ((t4>>24)&0x0f) == 0 ) { - data32 = 0x00335566; /* ESSS */ - break; - } - data32 = 0x77bbddee; /* SSSS */ - break; - } - if ((t4 & 0x0f) == 2) { - if ( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00003132; /* EEED */ - break; - } - if ( ((t4>>8)&0x0f) == 2 ) { - data32 = 0xb373ecdc; /* EEDD */ - break; - } - if ( ((t4>>16)&0x0f) == 0 ) { - data32 = 0x00b3a898; /* EESD */ - break; - } - data32 = 0x777becdc; /* ESSD */ - break; - } - die("Error - First dimm slot empty\n"); - } - - printk(BIOS_DEBUG, "ODT Value = %08x\n", data32); - - pci_write_config32(ctrl->f0, DDR2ODTC, data32); - - for (dimm = 0;dimm < 8;dimm+=2) { - - write32(MCBAR+DCALADDR, 0x0b840001); - write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20)); - - for (i = 0; i < 1001; i++) { - data32 = read32(MCBAR+DCALCSR); - if (!(data32 & (1<<31))) - break; - } - } -} -static void set_receive_enable(const struct mem_controller *ctrl) -{ - u32 i; - u32 cnt; - u32 recena = 0; - u32 recenb = 0; - - { - u32 dimm; - u32 edge; - int32_t data32; - u32 dcal_data32_0; - u32 dcal_data32_1; - u32 dcal_data32_2; - u32 dcal_data32_3; - u32 work32l; - u32 work32h; - u32 data32r; - int32_t recen; - for (dimm = 0;dimm < 8;dimm+=1) { - - if (!(dimm & 1)) { - write32(MCBAR+DCALDATA+(17*4), 0x04020000); - write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20)); - - for (i = 0; i < 1001; i++) { - data32 = read32(MCBAR+DCALCSR); - if (!(data32 & (1<<31))) - break; - } - if (i >= 1000) - continue; - - dcal_data32_0 = read32(MCBAR+DCALDATA + 0); - dcal_data32_1 = read32(MCBAR+DCALDATA + 4); - dcal_data32_2 = read32(MCBAR+DCALDATA + 8); - dcal_data32_3 = read32(MCBAR+DCALDATA + 12); - } - else { - dcal_data32_0 = read32(MCBAR+DCALDATA + 16); - dcal_data32_1 = read32(MCBAR+DCALDATA + 20); - dcal_data32_2 = read32(MCBAR+DCALDATA + 24); - dcal_data32_3 = read32(MCBAR+DCALDATA + 28); - } - - /* check if bank is installed */ - if ((dcal_data32_0 == 0) && (dcal_data32_2 == 0)) - continue; - /* Calculate the timing value */ - { - u32 bit; - for (i = 0,edge = 0,bit = 63,cnt = 31,data32r = 0, - work32l = dcal_data32_1,work32h = dcal_data32_3; - (i < 4) && bit; i++) { - for (;;bit--,cnt--) { - if (work32l & (1<<cnt)) - break; - if (!cnt) { - work32l = dcal_data32_0; - work32h = dcal_data32_2; - cnt = 32; - } - if (!bit) break; - } - for (;;bit--,cnt--) { - if (!(work32l & (1<<cnt))) - break; - if (!cnt) { - work32l = dcal_data32_0; - work32h = dcal_data32_2; - cnt = 32; - } - if (!bit) break; - } - if (!bit) { - break; - } - data32 = ((bit%8) << 1); - if (work32h & (1<<cnt)) - data32 += 1; - if (data32 < 4) { - if (!edge) { - edge = 1; - } - else { - if (edge != 1) { - data32 = 0x0f; - } - } - } - if (data32 > 12) { - if (!edge) { - edge = 2; - } - else { - if (edge != 2) { - data32 = 0x00; - } - } - } - data32r += data32; - } - } - work32l = dcal_data32_0; - work32h = dcal_data32_2; - recen = data32r; - recen += 3; - recen = recen>>2; - for (cnt = 5; cnt < 24;) { - for (;; cnt++) - if (!(work32l & (1<<cnt))) - break; - for (;; cnt++) { - if (work32l & (1<<cnt)) - break; - } - data32 = (((cnt-1)%8)<<1); - if (work32h & (1<<(cnt-1))) { - data32++; - } - /* test for frame edge cross overs */ - if ((edge == 1) && (data32 > 12) && - (((recen+16)-data32) < 3)) { - data32 = 0; - cnt += 2; - } - if ((edge == 2) && (data32 < 4) && - ((recen - data32) > 12)) { - data32 = 0x0f; - cnt -= 2; - } - if (((recen+3) >= data32) && ((recen-3) <= data32)) - break; - } - cnt--; - cnt /= 8; - cnt--; - if (recen & 1) - recen+=2; - recen >>= 1; - recen += (cnt*8); - recen+=2; /* this is not in the spec, but matches - the factory output, and has less failure */ - recen <<= (dimm/2) * 8; - if (!(dimm & 1)) { - recena |= recen; - } - else { - recenb |= recen; - } - } - } - /* Check for Errata problem */ - for (i = cnt = 0; i < 32; i+=8) { - if (((recena>>i)&0x0f)>7) { - cnt+= 0x101; - } - else { - if ((recena>>i)&0x0f) { - cnt++; - } - } - } - if (cnt & 0x0f00) { - cnt = (cnt & 0x0f) - (cnt>>16); - if (cnt > 1) { - for (i = 0; i < 32; i+=8) { - if (((recena>>i)&0x0f)>7) { - recena &= ~(0x0f<<i); - recena |= (7<<i); - } - } - } - else { - for (i = 0; i < 32; i+=8) { - if (((recena>>i)&0x0f)<8) { - recena &= ~(0x0f<<i); - recena |= (8<<i); - } - } - } - } - for (i = cnt = 0; i < 32; i+=8) { - if (((recenb>>i)&0x0f)>7) { - cnt+= 0x101; - } - else { - if ((recenb>>i)&0x0f) { - cnt++; - } - } - } - if (cnt & 0x0f00) { - cnt = (cnt & 0x0f) - (cnt>>16); - if (cnt > 1) { - for (i = 0; i < 32; i+=8) { - if (((recenb>>i)&0x0f)>7) { - recenb &= ~(0x0f<<i); - recenb |= (7<<i); - } - } - } - else { - for (i = 0; i < 32; i+=8) { - if (((recenb>>8)&0x0f)<8) { - recenb &= ~(0x0f<<i); - recenb |= (8<<i); - } - } - } - } - - printk(BIOS_DEBUG, "Receive enable A = %08x, Receive enable B = %08x\n", - recena, recenb); - - /* clear out the calibration area */ - write32(MCBAR+DCALDATA+(16*4), 0x00000000); - write32(MCBAR+DCALDATA+(17*4), 0x00000000); - write32(MCBAR+DCALDATA+(18*4), 0x00000000); - write32(MCBAR+DCALDATA+(19*4), 0x00000000); - - /* No command */ - write32(MCBAR+DCALCSR, 0x0000000f); - - write32(MCBAR+0x150, recena); - write32(MCBAR+0x154, recenb); -} - -static void cache_ramstage(void) -{ - /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ - disable_cache(); - set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - enable_cache(); -} - -static void sdram_enable(int controllers, const struct mem_controller *ctrl) -{ - int i; - int cs; - int cnt; - u8 *cntptr; - int cas_latency; - long mask; - u32 drc; - u32 data32; - u32 mode_reg; - const u32 *iptr; - u16 data16; - static const struct { - u32 clkgr[4]; - } gearing [] = { - /* FSB 100 */ - {{ 0x00000010, 0x00000000, 0x00000002, 0x00000001}}, - /* FSB 133 */ - {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}}, - /* FSB 167 */ - {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}}, - /* FSB 200 DIMM 400 */ - {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}}, - }; - - static const u32 dqs_data[] = { - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff}; - - mask = spd_detect_dimms(ctrl); - printk(BIOS_DEBUG, "Starting SDRAM Enable\n"); - - /* 0x80 */ - pci_write_config32(ctrl->f0, DRM, - 0x00410000 | CONFIG_DIMM_MAP_LOGICAL); - /* set dram type and Front Side Bus freq. */ - drc = spd_set_dram_controller_mode(ctrl, mask); - if ( drc == 0) { - die("Error calculating DRC\n"); - } - data32 = drc & ~(3 << 20); /* clear ECC mode */ - data32 = data32 & ~(7 << 8); /* clear refresh rates */ - data32 = data32 | (1 << 5); /* temp turn off ODT */ - /* Set gearing, then dram controller mode */ - /* drc bits 3:2 = FSB speed */ - for (iptr = gearing[(drc>>2)&3].clkgr,cnt = 0; cnt < 4; cnt++) { - pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]); - } - /* 0x7c DRC */ - pci_write_config32(ctrl->f0, DRC, data32); - - /* turn the clocks on */ - /* 0x8c CKDIS */ - pci_write_config16(ctrl->f0, CKDIS, 0x0000); - - /* 0x9a DDRCSR Take subsystem out of idle */ - data16 = pci_read_config16(ctrl->f0, DDRCSR); - data16 &= ~(7 << 12); - data16 |= (1 << 12); - pci_write_config16(ctrl->f0, DDRCSR, data16); - - /* program row size DRB */ - spd_set_ram_size(ctrl, mask); - - /* program page size DRA */ - spd_set_row_attributes(ctrl, mask); - - /* program DRT timing values */ - cas_latency = spd_set_drt_attributes(ctrl, mask, drc); - - for (i = 0; i < 8; i+=2) { /* loop through each dimm to test */ - printk(BIOS_DEBUG, "DIMM %08x\n", i); - /* Apply NOP */ - do_delay(); - - write32(MCBAR+DCALCSR, (0x01000000 | (i<<20))); - write32(MCBAR+DCALCSR, (0x81000000 | (i<<20))); - - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Apply NOP */ - do_delay(); - - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Precharge all banks */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, 0x04000000); - write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* EMRS dll's enabled */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - /* fixme hard code AL additive latency */ - write32(MCBAR+DCALADDR, 0x0b940001); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - /* MRS reset dll's */ - do_delay(); - if (cas_latency == 30) - mode_reg = 0x053a0000; - else - mode_reg = 0x054a0000; - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, mode_reg); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Precharge all banks */ - do_delay(); - do_delay(); - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, 0x04000000); - write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Do 2 refreshes */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - do_delay(); - /* for good luck do 6 more */ - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - } - do_delay(); - /* MRS reset dll's normal */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24))); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Do only if DDR2 EMRS dll's enabled */ - do_delay(); - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALADDR, (0x0b940001)); - write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - do_delay(); - /* No command */ - write32(MCBAR+DCALCSR, 0x0000000f); - - /* enable on dimm termination */ - set_on_dimm_termination_enable(ctrl); - - /* receive enable calibration */ - set_receive_enable(ctrl); - - /* DQS */ - pci_write_config32(ctrl->f0, 0x94, 0x3904aa00); - for (i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) { - write32(cntptr, dqs_data[i]); - } - pci_write_config32(ctrl->f0, 0x94, 0x3900aa00); - - /* Enable refresh */ - /* 0x7c DRC */ - data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); - write32(MCBAR+DCALCSR, 0x0008000f); - - /* clear memory and init ECC */ - printk(BIOS_DEBUG, "Clearing memory\n"); - for (i = 0; i < 64; i+=4) { - write32(MCBAR+DCALDATA+i, 0x00000000); - } - - for (cs = 0; cs < 8; cs+=2) { - write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20))); - do data32 = read32(MCBAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Bring memory subsystem on line */ - data32 = pci_read_config32(ctrl->f0, 0x98); - data32 |= (1 << 31); - pci_write_config32(ctrl->f0, 0x98, data32); - /* wait for completion */ - printk(BIOS_DEBUG, "Waiting for mem complete\n"); - while (1) { - data32 = pci_read_config32(ctrl->f0, 0x98); - if ( (data32 & (1<<31)) == 0) - break; - } - printk(BIOS_DEBUG, "Done\n"); - - /* Set initialization complete */ - /* 0x7c DRC */ - drc |= (1 << 29); - data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); - - /* Set the ecc mode */ - pci_write_config32(ctrl->f0, DRC, drc); - - /* Enable memory scrubbing */ - /* 0x52 MCHSCRB */ - data16 = pci_read_config16(ctrl->f0, MCHSCRB); - data16 &= ~0x0f; - data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(ctrl->f0, MCHSCRB, data16); - - /* The memory is now setup, use it */ - if (!IS_ENABLED(CONFIG_CACHE_AS_RAM)) - cache_ramstage(); -} diff --git a/src/northbridge/intel/i3100/raminit.h b/src/northbridge/intel/i3100/raminit.h deleted file mode 100644 index aa245deba5..0000000000 --- a/src/northbridge/intel/i3100/raminit.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This code is based on src/northbridge/intel/e7520/raminit.h */ - -#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_H -#define NORTHBRIDGE_INTEL_I3100_RAMINIT_H - -#define DIMM_SOCKETS 4 -struct mem_controller { - u32 node_id; - device_t f0, f1, f2, f3; - u16 channel0[DIMM_SOCKETS]; - u16 channel1[DIMM_SOCKETS]; -}; - -void sdram_initialize(int controllers, const struct mem_controller *ctrl); - -#endif diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c deleted file mode 100644 index fa557da0f1..0000000000 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ /dev/null @@ -1,693 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <lib.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/intel/speedstep.h> -#include <lib.h> -#include <delay.h> -#include "raminit_ep80579.h" -#include "ep80579.h" - -#define BAR ((u8 *)0x90000000) - -static void sdram_set_registers(const struct mem_controller *ctrl) -{ - static const u32 register_values[] = { - PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG, - PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, - PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, - PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a, - PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0, - }; - int i; - - for (i = 0; i < ARRAY_SIZE(register_values); i += 3) { - device_t dev; - u32 where; - u32 reg; - dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; - where = register_values[i] & 0xff; - reg = pci_read_config32(dev, where); - reg &= register_values[i+1]; - reg |= register_values[i+2]; - pci_write_config32(dev, where, reg); - } -} - -struct dimm_size { - u32 side1; - u32 side2; -}; - -static struct dimm_size spd_get_dimm_size(u16 device) -{ - /* Calculate the log base 2 size of a DIMM in bits */ - struct dimm_size sz; - int value, low; - sz.side1 = 0; - sz.side2 = 0; - - /* Note it might be easier to use byte 31 here, it has the DIMM size as - * a multiple of 4MB. The way we do it now we can size both - * sides of an assymetric dimm. - */ - value = spd_read_byte(device, SPD_NUM_ROWS); - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - sz.side1 += value & 0xf; - - value = spd_read_byte(device, SPD_NUM_COLUMNS); - if (value < 0) goto hw_err; - if ((value & 0xf) == 0) goto val_err; - sz.side1 += value & 0xf; - - value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side1 += log2(value & 0xff); - - /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); - if (value < 0) goto hw_err; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); - if (low < 0) goto hw_err; - value = value | (low & 0xff); - if ((value != 72) && (value != 64)) goto val_err; - sz.side1 += log2(value); - - /* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); - - if (value < 0) goto hw_err; - value &= 7; - value++; - if (value == 1) goto out; - if (value != 2) goto val_err; - - /* Start with the symmetrical case */ - sz.side2 = sz.side1; - - value = spd_read_byte(device, SPD_NUM_ROWS); - if (value < 0) goto hw_err; - if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */ - sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */ - sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */ - - value = spd_read_byte(device, SPD_NUM_COLUMNS); - if (value < 0) goto hw_err; - if ((value & 0xff) == 0) goto val_err; - sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */ - sz.side2 += ((value >> 4) & 0x0f); /* Add in columns on side 2 */ - goto out; - - val_err: - die("Bad SPD value\n"); - /* If an hw_error occurs report that I have no memory */ - hw_err: - sz.side1 = 0; - sz.side2 = 0; -out: - printk(BIOS_DEBUG, "dimm %02x size = %02x.%02x\n", device, sz.side1, sz.side2); - return sz; - -} - -static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask) -{ - int i; - int cum; - - for (i = cum = 0; i < DIMM_SOCKETS; i++) { - struct dimm_size sz; - if (dimm_mask & (1 << i)) { - sz = spd_get_dimm_size(ctrl->channel0[i]); - if (sz.side1 < 29) { - return -1; /* Report SPD error */ - } - /* convert bits to multiples of 64MB */ - sz.side1 -= 29; - cum += (1 << sz.side1); - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); - if (spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS) & 0x1) { - cum <<= 1; - } - } - else { - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); - } - } - printk(BIOS_DEBUG, "DRB = %08x\n", pci_read_config32(ctrl->f0, DRB)); - - cum >>= 1; - /* set TOM top of memory */ - pci_write_config16(ctrl->f0, TOM, cum); - printk(BIOS_DEBUG, "TOM = %04x\n", cum); - /* set TOLM top of low memory */ - if (cum > 0x18) { - cum = 0x18; - } - cum <<= 11; - pci_write_config16(ctrl->f0, TOLM, cum); - printk(BIOS_DEBUG, "TOLM = %04x\n", cum); - return 0; -} - - -static u8 spd_detect_dimms(const struct mem_controller *ctrl) -{ - u8 dimm_mask = 0; - int i; - for (i = 0; i < DIMM_SOCKETS; i++) { - int byte; - u16 device; - device = ctrl->channel0[i]; - if (device) { - byte = spd_read_byte(device, SPD_MEMORY_TYPE); - printk(BIOS_DEBUG, "spd %02x = %02x\n", device, byte); - if (byte == 8) { - dimm_mask |= (1 << i); - } - } - } - return dimm_mask; -} - - -static int spd_set_row_attributes(const struct mem_controller *ctrl, - u8 dimm_mask) -{ - int value; - int i; - - for (i = 0; i < DIMM_SOCKETS; i++) { - u32 dra = 0; - int reg = 0; - - if (!(dimm_mask & (1 << i))) { - continue; - } - - value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS); - if (value < 0) die("Bad SPD data\n"); - if ((value & 0xf) == 0) die("Invalid # of rows\n"); - dra |= (((value-13) & 0x7) << 23); - dra |= (((value-13) & 0x7) << 29); - reg += value & 0xf; - - value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS); - if (value < 0) die("Bad SPD data\n"); - if ((value & 0xf) == 0) die("Invalid # of columns\n"); - dra |= (((value-10) & 0x7) << 20); - dra |= (((value-10) & 0x7) << 26); - reg += value & 0xf; - - value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM); - if (value < 0) die("Bad SPD data\n"); - if ((value & 0xff) == 0) die("Invalid # of banks\n"); - reg += log2(value & 0xff); - - printk(BIOS_DEBUG, "dimm %02x reg = %02x\n", i, reg); - - /* set device density */ - dra |= ((31-reg)); - dra |= ((31-reg) << 6); - - /* set device width (x8) */ - dra |= (1 << 4); - dra |= (1 << 10); - - /* set device type (registered) */ - dra |= (1 << 14); - - /* set number of ranks (0 = single, 1 = dual) */ - value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS); - dra |= ((value & 0x1) << 17); - - printk(BIOS_DEBUG, "DRA%02x = %08x\n", i, dra); - - pci_write_config32(ctrl->f0, DRA + (i*4), dra); - } - return 0; -} - - -static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, - u8 dimm_mask, u32 drc) -{ - int i; - u32 val, val1; - u32 cl; - u32 trc = 0; - u32 trfc = 0; - u32 tras = 0; - u32 trtp = 0; - u32 twtr = 0; - int index = drc & 0x00000003; - int ci; - static const u8 latencies[] = { /* 533, 800, 400, 667 */ - 0x10, 0x60, 0x10, 0x20 }; - static const u32 drt0[] = { /* 533, 800, 400, 667 */ - 0x24240002, 0x24360002, 0x24220002, 0x24360002 }; - static const u32 drt1[] = { /* 533, 800, 400, 667 */ - 0x00400000, 0x00900000, 0x00200000, 0x00700000 }; - static const u32 magic[] = { /* 533, 800, 400, 667 */ - 0x007b8221, 0x00b94331, 0x005ca1a1, 0x009a62b1 }; - static const u32 mrs[] = { /* 533, 800, 400, 667 */ - 0x07020000, 0x0b020000, 0x05020000, 0x09020000 }; - static const int cycle[] = { /* 533, 800, 400, 667 */ - 15, 10, 20, 12 }; /* cycle time in 1/4 ns units */ - static const int byte40rem[] = { - 0, 1, 2, 2, 3, 3, 0, 0 }; /* byte 40 remainder in 1/4 ns units */ - - /* CAS latency in cycles */ - val = latencies[index]; - for (i = 0; i < DIMM_SOCKETS; i++) { - if (!(dimm_mask & (1 << i))) - continue; - val &= spd_read_byte(ctrl->channel0[i], SPD_ACCEPTABLE_CAS_LATENCIES); - } - if (val & 0x10) - cl = 4; - else if (val & 0x20) - cl = 5; - else if (val & 0x40) - cl = 6; - else - die("CAS latency mismatch\n"); - printk(BIOS_DEBUG, "cl = %02x\n", cl); - - ci = cycle[index]; - - /* Trc, Trfc in cycles */ - for (i = 0; i < DIMM_SOCKETS; i++) { - if (!(dimm_mask & (1 << i))) - continue; - val1 = spd_read_byte(ctrl->channel0[i], SPD_BYTE_41_42_EXTENSION); - val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACT_TO_ACT_AUTO_REFRESH); - val <<= 2; /* convert to 1/4 ns */ - val += byte40rem[(val1 >> 4) & 0x7]; - val = CEIL_DIV(val, ci) + 1; /* convert to cycles */ - if (trc < val) - trc = val; - val = spd_read_byte(ctrl->channel0[i], SPD_MIN_AUTO_REFRESH_TO_ACT); - val <<= 2; /* convert to 1/4 ns */ - if (val1 & 0x01) - val += 1024; - val += byte40rem[(val1 >> 1) & 0x7]; - val = CEIL_DIV(val, ci); /* convert to cycles */ - if (trfc < val) - trfc = val; - } - printk(BIOS_DEBUG, "trc = %02x\n", trc); - printk(BIOS_DEBUG, "trfc = %02x\n", trfc); - - /* Tras, Trtp, Twtr in cycles */ - for (i = 0; i < DIMM_SOCKETS; i++) { - if (!(dimm_mask & (1 << i))) - continue; - val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - val <<= 2; /* convert to 1/4 ns */ - val = CEIL_DIV(val, ci); /* convert to cycles */ - if (tras < val) - tras = val; - val = spd_read_byte(ctrl->channel0[i], SPD_INT_READ_TO_PRECHARGE_DELAY); - val = CEIL_DIV(val, ci); /* convert to cycles */ - if (trtp < val) - trtp = val; - val = spd_read_byte(ctrl->channel0[i], SPD_INT_WRITE_TO_READ_DELAY); - val = CEIL_DIV(val, ci); /* convert to cycles */ - if (twtr < val) - twtr = val; - } - printk(BIOS_DEBUG, "tras = %02x\n", tras); - printk(BIOS_DEBUG, "trtp = %02x\n", trtp); - printk(BIOS_DEBUG, "twtr = %02x\n", twtr); - - val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9) - | ((cl - 3) << 6) | ((cl - 3) << 3)); - printk(BIOS_DEBUG, "drt0 = %08x\n", val); - pci_write_config32(ctrl->f0, DRT0, val); - - val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25) - | (twtr << 15)); - printk(BIOS_DEBUG, "drt1 = %08x\n", val); - pci_write_config32(ctrl->f0, DRT1, val); - - val = (magic[index]); - printk(BIOS_DEBUG, "magic = %08x\n", val); - pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val); - - val = (mrs[index] | (cl << 20)); - printk(BIOS_DEBUG, "mrs = %08x\n", val); - return val; -} - -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, - u8 dimm_mask) -{ - int value; - int drc = 0; - int i; - msr_t msr; - u8 cycle = 0x25; - - for (i = 0; i < DIMM_SOCKETS; i++) { - if (!(dimm_mask & (1 << i))) - continue; - if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40) - die("ERROR: Only 64-bit DIMMs supported\n"); - if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02)) - die("ERROR: Only ECC DIMMs supported\n"); - if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08) - die("ERROR: Only x8 DIMMs supported\n"); - - value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (value > cycle) - cycle = value; - } - printk(BIOS_DEBUG, "cycle = %02x\n", cycle); - - drc |= (1 << 20); /* enable ECC */ - drc |= (3 << 30); /* enable CKE on each DIMM */ - drc |= (1 << 4); /* enable CKE globally */ - - /* TODO check: */ - /* set front side bus speed */ - msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */ - printk(BIOS_DEBUG, "MSR FSB_FREQ(0xcd) = %08x%08x\n", msr.hi, msr.lo); - - /* TODO check that this msr really indicates fsb speed! */ - if (msr.lo & 0x07) { - printk(BIOS_INFO, "533 MHz FSB\n"); - if (cycle <= 0x25) { - drc |= 0x5; - printk(BIOS_INFO, "400 MHz DDR\n"); - } else if (cycle <= 0x30) { - drc |= 0x7; - printk(BIOS_INFO, "333 MHz DDR\n"); - } else if (cycle <= 0x3d) { - drc |= 0x4; - printk(BIOS_INFO, "266 MHz DDR\n"); - } else { - drc |= 0x2; - printk(BIOS_INFO, "200 MHz DDR\n"); - } - } - else { - printk(BIOS_INFO, "400 MHz FSB\n"); - if (cycle <= 0x30) { - drc |= 0x7; - printk(BIOS_INFO, "333 MHz DDR\n"); - } else if (cycle <= 0x3d) { - drc |= 0x0; - printk(BIOS_INFO, "266 MHz DDR\n"); - } else { - drc |= 0x2; - printk(BIOS_INFO, "200 MHz DDR\n"); - } - } - - printk(BIOS_DEBUG, "DRC = %08x\n", drc); - - return drc; -} - -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - u8 dimm_mask; - - /* Test if we can read the SPD */ - dimm_mask = spd_detect_dimms(ctrl); - if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - printk(BIOS_ERR, "No memory for this cpu\n"); - return; - } - return; -} - -static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) -{ - u8 c1,c2; - u32 i; - u32 data32 = 0; - - /* Set up northbridge values */ - /* ODT enable */ - pci_write_config32(ctrl->f0, SDRC, 0xa0002c30); - - c1 = pci_read_config8(ctrl->f0, DRB); - c2 = pci_read_config8(ctrl->f0, DRB+2); - if (c1 == c2) { - /* 1 single-rank DIMM */ - data32 = 0x00000010; - } - else { - /* 2 single-rank DIMMs or 1 double-rank DIMM */ - data32 = 0x00002010; - } - - printk(BIOS_DEBUG, "ODT Value = %08x\n", data32); - - pci_write_config32(ctrl->f0, DDR2ODTC, data32); - - for (i = 0; i < 2; i++) { - printk(BIOS_DEBUG, "ODT CS%d\n", i); - - write32(BAR+DCALADDR, 0x0b840001); - write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21)); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } -} - - -static void dump_dcal_regs(void) -{ - int i; - for (i = 0x0; i < 0x2a0; i += 4) { - if ((i % 16) == 0) { - printk(BIOS_DEBUG, "\n%04x: ", i); - } - printk(BIOS_DEBUG, "%08x ", read32(BAR+i)); - } - printk(BIOS_DEBUG, "\n"); -} - - -static void sdram_enable(int controllers, const struct mem_controller *ctrl) -{ - int i; - int cs; - long mask; - u32 drc; - u32 data32; - u32 mode_reg; - - mask = spd_detect_dimms(ctrl); - printk(BIOS_DEBUG, "Starting SDRAM Enable\n"); - - /* Set DRAM type and Front Side Bus frequency */ - drc = spd_set_dram_controller_mode(ctrl, mask); - if (drc == 0) { - die("Error calculating DRC\n"); - } - data32 = drc & ~(3 << 20); /* clear ECC mode */ - data32 = data32 | (3 << 5); /* temp turn off ODT */ - /* Set DRAM controller mode */ - pci_write_config32(ctrl->f0, DRC, data32); - - /* Turn the clocks on */ - pci_write_config16(ctrl->f0, CKDIS, 0x0000); - - /* Program row size */ - spd_set_ram_size(ctrl, mask); - - /* Program row attributes */ - spd_set_row_attributes(ctrl, mask); - - /* Program timing values */ - mode_reg = spd_set_drt_attributes(ctrl, mask, drc); - - dump_dcal_regs(); - - /* Apply NOP */ - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "NOP CS%d\n", cs); - udelay(16); - write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21))); - write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Apply NOP */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "NOP CS%d\n", cs); - write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Precharge all banks */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "Precharge CS%d\n", cs); - write32(BAR+DCALADDR, 0x04000000); - write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* EMRS: Enable DLLs, set OCD calibration mode to default */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "EMRS CS%d\n", cs); - write32(BAR+DCALADDR, 0x0b840001); - write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - /* MRS: Reset DLLs */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "MRS CS%d\n", cs); - write32(BAR+DCALADDR, mode_reg); - write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Precharge all banks */ - udelay(48); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "Precharge CS%d\n", cs); - write32(BAR+DCALADDR, 0x04000000); - write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* Do 2 refreshes */ - for (i = 0; i < 2; i++) { - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "Refresh CS%d\n", cs); - write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - } - - /* MRS: Set DLLs to normal */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "MRS CS%d\n", cs); - write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); - write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - /* EMRS: Enable DLLs */ - udelay(16); - for (cs = 0; cs < 2; cs++) { - printk(BIOS_DEBUG, "EMRS CS%d\n", cs); - write32(BAR+DCALADDR, 0x0b840001); - write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - udelay(16); - /* No command */ - write32(BAR+DCALCSR, 0x0000000f); - - write32(BAR, 0x00100000); - - /* Enable on-DIMM termination */ - set_on_dimm_termination_enable(ctrl); - - dump_dcal_regs(); - - /* Receive enable calibration */ - udelay(16); - for (cs = 0; cs < 1; cs++) { - printk(BIOS_DEBUG, "receive enable calibration CS%d\n", cs); - write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21))); - do data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000); - } - - dump_dcal_regs(); - - /* Adjust RCOMP */ - data32 = read32(BAR+DDRIOMC2); - data32 &= ~(0xf << 16); - data32 |= (0xb << 16); - write32(BAR+DDRIOMC2, data32); - - dump_dcal_regs(); - - data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); - write32(BAR+DCALCSR, 0x0008000f); - - /* Clear memory and init ECC */ - for (cs = 0; cs < 2; cs++) { - if (!(mask & (1<<cs))) - continue; - printk(BIOS_DEBUG, "clear memory CS%d\n", cs); - write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16)); - do data32 = read32(BAR+MBCSR); - while (data32 & 0x80000000); - if (data32 & 0x40000000) - printk(BIOS_DEBUG, "failed!\n"); - } - - /* Clear read/write FIFO pointers */ - printk(BIOS_DEBUG, "clear read/write fifo pointers\n"); - write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15)); - udelay(16); - write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15)); - udelay(16); - - dump_dcal_regs(); - - printk(BIOS_DEBUG, "Done\n"); - - /* Set initialization complete */ - drc |= (1 << 29); - drc |= (3 << 30); - data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); - - /* Set the ECC mode */ - pci_write_config32(ctrl->f0, DRC, drc); -} - -static inline int memory_initialized(void) -{ - return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) & (1 << 29); -} diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h deleted file mode 100644 index aca96d2a25..0000000000 --- a/src/northbridge/intel/i3100/raminit_ep80579.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H -#define NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H - -#define DIMM_SOCKETS 2 -struct mem_controller { - u32 node_id; - device_t f0; - u16 channel0[DIMM_SOCKETS]; -}; - -void sdram_initialize(int controllers, const struct mem_controller *ctrl); -#endif diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c deleted file mode 100644 index 1ea62c0a6c..0000000000 --- a/src/northbridge/intel/i3100/reset_test.c +++ /dev/null @@ -1,20 +0,0 @@ -/* Convert to C by yhlu */ -#define MCH_DRC 0x7c -#define DRC_DONE (1 << 29) - -/* If I have already booted once skip a bunch of initialization */ -/* To see if I have already booted I check to see if memory - * has been enabled. - */ -int bios_reset_detected(void) -{ - uint32_t dword; - - dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - - if ( (dword & DRC_DONE) != 0 ) { - return 1; - } - - return 0; -} diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig deleted file mode 100644 index 20990ba289..0000000000 --- a/src/southbridge/intel/i3100/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -config SOUTHBRIDGE_INTEL_I3100 - bool - select IOAPIC - select HAVE_HARD_RESET - select SOUTHBRIDGE_INTEL_COMMON - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - -if SOUTHBRIDGE_INTEL_I3100 - -config HPET_MIN_TICKS - hex - default 0x90 - -endif diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc deleted file mode 100644 index bcc6d06171..0000000000 --- a/src/southbridge/intel/i3100/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I3100),y) - -ramstage-y += i3100.c -ramstage-y += uhci.c -ramstage-y += lpc.c -ramstage-y += sata.c -ramstage-y += ehci.c -ramstage-y += smbus.c -ramstage-y += pci.c -ramstage-y += ioapic.c -ramstage-y += reset.c -ramstage-y += pciexp_portb.c - -endif diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h deleted file mode 100644 index 26a452a195..0000000000 --- a/src/southbridge/intel/i3100/chip.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -struct southbridge_intel_i3100_config -{ -#define I3100_GPIO_USE_MASK 0x03 -#define I3100_GPIO_USE_DEFAULT 0x00 -#define I3100_GPIO_USE_AS_NATIVE 0x01 -#define I3100_GPIO_USE_AS_GPIO 0x02 - -#define I3100_GPIO_SEL_MASK 0x0c -#define I3100_GPIO_SEL_DEFAULT 0x00 -#define I3100_GPIO_SEL_OUTPUT 0x04 -#define I3100_GPIO_SEL_INPUT 0x08 - -#define I3100_GPIO_LVL_MASK 0x30 -#define I3100_GPIO_LVL_DEFAULT 0x00 -#define I3100_GPIO_LVL_LOW 0x10 -#define I3100_GPIO_LVL_HIGH 0x20 -#define I3100_GPIO_LVL_BLINK 0x30 - -#define I3100_GPIO_INV_MASK 0xc0 -#define I3100_GPIO_INV_DEFAULT 0x00 -#define I3100_GPIO_INV_OFF 0x40 -#define I3100_GPIO_INV_ON 0x80 - - /* GPIO use select */ - u8 gpio[64]; - int sata_ports_implemented; - u32 pirq_a_d; - u32 pirq_e_h; -}; diff --git a/src/southbridge/intel/i3100/early_lpc.c b/src/southbridge/intel/i3100/early_lpc.c deleted file mode 100644 index bd9d974c69..0000000000 --- a/src/southbridge/intel/i3100/early_lpc.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -static void i3100_enable_superio(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Enable decoding of I/O locations for SuperIO devices */ - pci_write_config16(dev, 0x80, 0x0010); - pci_write_config16(dev, 0x82, 0x340f); - - /* Enable the SERIRQs (start pulse width is 8 clock cycles) */ - pci_write_config8(dev, 0x64, 0xD2); -} - -static void i3100_halt_tco_timer(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Temporarily enable the ACPI I/O range at 0x4000 */ - pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); - pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); - - /* Halt the TCO timer, preventing SMI and automatic reboot */ - outw(inw(0x4068) | (1 << 11), 0x4068); - - /* Disable the ACPI I/O range */ - pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7)); -} diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c deleted file mode 100644 index 35fe614d8e..0000000000 --- a/src/southbridge/intel/i3100/early_smbus.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <southbridge/intel/common/smbus.h> - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - printk(BIOS_SPEW, "SMBus controller enabled\n"); - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - pci_write_config8(dev, 0x40, 1); - pci_write_config8(dev, 0x4, 1); - /* SMBALERT_DIS */ - outb(4, SMBUS_IO_BASE + SMBSLVCMD); - - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); -} - -static __attribute__((unused)) int smbus_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -static __attribute__((unused)) int smbus_write_byte(unsigned device, u8 address, u8 data) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); -} diff --git a/src/southbridge/intel/i3100/ehci.c b/src/southbridge/intel/i3100/ehci.c deleted file mode 100644 index e8809d8815..0000000000 --- a/src/southbridge/intel/i3100/ehci.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - -static void ehci_init(struct device *dev) -{ -} - -static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - u8 access_cntl; - access_cntl = pci_read_config8(dev, 0x80); - /* Enable writes to protected registers */ - pci_write_config8(dev, 0x80, access_cntl | 1); - /* Write the subsystem vendor and device id */ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - /* Restore protection */ - pci_write_config8(dev, 0x80, access_cntl); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &ehci_set_subsystem, -}; -static struct device_operations ehci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ehci_driver __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_EHCI, -}; - -static const struct pci_driver ehci_driver_ep80579 __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_EHCI, -}; diff --git a/src/southbridge/intel/i3100/i3100.c b/src/southbridge/intel/i3100/i3100.c deleted file mode 100644 index 7becc0e4e5..0000000000 --- a/src/southbridge/intel/i3100/i3100.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include "i3100.h" - -void i3100_enable(device_t dev) -{ - device_t lpc_dev; - u8 func; - volatile u32 *disable; - - if (dev->enabled) - return; - - /* - * To disable an integrated southbridge device, set the corresponding - * flag in the Function Disable register. - */ - - /* Temporarily enable the root complex register block at 0xa0000000. */ - lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0)); - pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0)); - disable = (volatile u32 *) 0xa0003418; - func = PCI_FUNC(dev->path.pci.devfn); - switch (PCI_SLOT(dev->path.pci.devfn)) { - case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */ - *disable |= (1 << (func == 0x0 ? 14 : func)); - break; - case 0x1d: /* UHCI (fn0, fn1), EHCI (fn7) */ - *disable |= (1 << (func + 8)); - break; - case 0x1c: /* PCIe ports B0-B3 (fn0-fn3) */ - *disable |= (1 << (func + 16)); - break; - } - /* Disable the root complex register block. */ - pci_write_config32(lpc_dev, 0xf0, 0); -} - -struct chip_operations southbridge_intel_i3100_ops = { - CHIP_NAME("Intel 3100 Southbridge") -}; diff --git a/src/southbridge/intel/i3100/i3100.h b/src/southbridge/intel/i3100/i3100.h deleted file mode 100644 index 297a2a688d..0000000000 --- a/src/southbridge/intel/i3100/i3100.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_INTEL_I3100_I3100_H -#define SOUTHBRIDGE_INTEL_I3100_I3100_H -#include "chip.h" - -#define SATA_CMD 0x04 -#define SATA_PI 0x09 -#define SATA_PTIM 0x40 -#define SATA_STIM 0x42 -#define SATA_D1TIM 0x44 -#define SATA_SYNCC 0x48 -#define SATA_SYNCTIM 0x4A -#define SATA_IIOC 0x54 -#define SATA_MAP 0x90 -#define SATA_PCS 0x91 -#define SATA_ACR0 0xA8 -#define SATA_ACR1 0xAC -#define SATA_ATC 0xC0 -#define SATA_ATS 0xC4 -#define SATA_SP 0xD0 - -#define SATA_MODE_IDE 0x00 -#define SATA_MODE_AHCI 0x01 - -#ifndef __SIMPLE_DEVICE__ -void i3100_enable(device_t dev); -#endif - -#endif diff --git a/src/southbridge/intel/i3100/ioapic.c b/src/southbridge/intel/i3100/ioapic.c deleted file mode 100644 index a324e7d3f4..0000000000 --- a/src/southbridge/intel/i3100/ioapic.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - - -static void read_resources(struct device *dev) -{ - u32 tmp; - - /* Enable IO(X)APIC config space */ - tmp = pci_read_config16(dev, 0x40); - pci_write_config16(dev, 0x40, tmp & ~(1 << 13)); - /* Enable I/O APIC space at 0xfec80000 */ - dev->path.pci.devfn |= 1; - pci_write_config16(dev, 0x04, 0x06); - pci_write_config32(dev, 0x10, 0xfec80000); - dev->path.pci.devfn &= ~1; - pci_write_config16(dev, 0x40, tmp); - - pci_bus_read_resources(dev); -} - -static struct device_operations pci_ops = { - .read_resources = read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, - -}; - -static const struct pci_driver pci_driver0 __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x3500, -}; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c deleted file mode 100644 index e3c463ba2a..0000000000 --- a/src/southbridge/intel/i3100/lpc.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Linux Networx - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/southbridge/intel/esb6300/esb6300_lpc.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> -#include <pc80/i8259.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <arch/acpi.h> -#include "i3100.h" - -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x48 -#define RCBA 0xf0 - -#define SERIRQ_CNTL 0x64 - -#define GEN_PMCON_1 0xA0 -#define GEN_PMCON_2 0xA2 -#define GEN_PMCON_3 0xA4 - -#define NMI_OFF 0 -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - -static void i3100_enable_serial_irqs(device_t dev) -{ - /* set packet length and toggle silent mode bit */ - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); - pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); -} - -typedef struct southbridge_intel_i3100_config config_t; - -static void set_i3100_gpio_use_sel( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_use_sel, gpio_use_sel2; - int i; - - gpio_use_sel = inl(res->base + 0x00) | 0x0000c603; - gpio_use_sel2 = inl(res->base + 0x30) | 0x00000100; - for (i = 0; i < 64; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_USE_MASK) { - case I3100_GPIO_USE_AS_NATIVE: - val = 0; - break; - case I3100_GPIO_USE_AS_GPIO: - val = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_use_sel &= ~(1 << i); - gpio_use_sel |= (val << i); - } else { - gpio_use_sel2 &= ~(1 << (i - 32)); - gpio_use_sel2 |= (val << (i - 32)); - } - } - outl(gpio_use_sel, res->base + 0x00); - outl(gpio_use_sel2, res->base + 0x30); -} - -static void set_i3100_gpio_direction( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_io_sel, gpio_io_sel2; - int i; - - gpio_io_sel = inl(res->base + 0x04); - gpio_io_sel2 = inl(res->base + 0x34); - for (i = 0; i < 64; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_SEL_MASK) { - case I3100_GPIO_SEL_OUTPUT: - val = 0; - break; - case I3100_GPIO_SEL_INPUT: - val = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_io_sel &= ~(1 << i); - gpio_io_sel |= (val << i); - } else { - gpio_io_sel2 &= ~(1 << (i - 32)); - gpio_io_sel2 |= (val << (i - 32)); - } - } - outl(gpio_io_sel, res->base + 0x04); - outl(gpio_io_sel2, res->base + 0x34); -} - -static void set_i3100_gpio_level( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_lvl, gpio_lvl2; - u32 gpio_blink; - int i; - - gpio_lvl = inl(res->base + 0x0c); - gpio_blink = inl(res->base + 0x18); - gpio_lvl2 = inl(res->base + 0x38); - for (i = 0; i < 64; i++) { - int val, blink; - switch (config->gpio[i] & I3100_GPIO_LVL_MASK) { - case I3100_GPIO_LVL_LOW: - val = 0; - blink = 0; - break; - case I3100_GPIO_LVL_HIGH: - val = 1; - blink = 0; - break; - case I3100_GPIO_LVL_BLINK: - val = 1; - blink = 1; - break; - default: - continue; - } - /* The caller is responsible for not playing with unimplemented bits */ - if (i < 32) { - gpio_lvl &= ~(1 << i); - gpio_blink &= ~(1 << i); - gpio_lvl |= (val << i); - gpio_blink |= (blink << i); - } else { - gpio_lvl2 &= ~(1 << (i - 32)); - gpio_lvl2 |= (val << (i - 32)); - } - } - outl(gpio_lvl, res->base + 0x0c); - outl(gpio_blink, res->base + 0x18); - outl(gpio_lvl2, res->base + 0x38); -} - -static void set_i3100_gpio_inv( - device_t dev, struct resource *res, config_t *config) -{ - u32 gpio_inv; - int i; - - gpio_inv = inl(res->base + 0x2c); - for (i = 0; i < 32; i++) { - int val; - switch (config->gpio[i] & I3100_GPIO_INV_MASK) { - case I3100_GPIO_INV_OFF: - val = 0; - break; - case I3100_GPIO_INV_ON: - val = 1; - break; - default: - continue; - } - gpio_inv &= ~(1 << i); - gpio_inv |= (val << i); - } - outl(gpio_inv, res->base + 0x2c); -} - -static void i3100_pirq_init(device_t dev) -{ - device_t irq_dev; - config_t *config; - - /* Get the chip configuration */ - config = dev->chip_info; - - if (config->pirq_a_d) - pci_write_config32(dev, 0x60, config->pirq_a_d); - - if (config->pirq_e_h) - pci_write_config32(dev, 0x68, config->pirq_e_h); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ - int_line = config->pirq_a_d & 0xff; - break; - - case 2: /* INTB# */ - int_line = (config->pirq_a_d >> 8) & 0xff; - break; - - case 3: /* INTC# */ - int_line = (config->pirq_a_d >> 16) & 0xff; - break; - - case 4: /* INTD# */ - int_line = (config->pirq_a_d >> 24) & 0xff; - break; - } - - if (!int_line) - continue; - - printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line); - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } - - -} - -static void i3100_power_options(device_t dev) { - u8 reg8; - u16 reg16; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - int nmi_option; - - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - get_option(&pwr_on, "power_on_after_fail"); - reg8 = pci_read_config8(dev, GEN_PMCON_3); - reg8 &= 0xfe; - if (pwr_on) { - reg8 &= ~1; - } else { - reg8 |= 1; - } - /* avoid #S4 assertions */ - reg8 |= (3 << 4); - /* minimum asssertion is 1 to 2 RTCCLK */ - reg8 &= ~(1 << 3); - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); - - /* Set up NMI on errors. */ - reg8 = inb(0x61); - /* Higher Nibble must be 0 */ - reg8 &= 0x0f; - /* IOCHK# NMI Enable */ - reg8 &= ~(1 << 3); - /* PCI SERR# Enable */ - // reg8 &= ~(1 << 2); - /* PCI SERR# Disable for now */ - reg8 |= (1 << 2); - outb(reg8, 0x61); - - reg8 = inb(0x70); - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - /* Set NMI. */ - printk(BIOS_INFO, "NMI sources enabled.\n"); - reg8 &= ~(1 << 7); - } else { - /* Can't mask NMI from PCI-E and NMI_NOW */ - printk(BIOS_INFO, "NMI sources disabled.\n"); - reg8 |= ( 1 << 7); - } - outb(reg8, 0x70); - - // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down - reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~((3 << 0) | (1 << 10)); - reg16 |= (1 << 3) | (1 << 5); - /* CLKRUN_EN */ - // reg16 |= (1 << 2); - pci_write_config16(dev, GEN_PMCON_1, reg16); - - // Set the board's GPI routing. - // i82801gx_gpi_routing(dev); -} - -static void i3100_gpio_init(device_t dev) -{ - struct resource *res; - config_t *config; - - /* Skip if I don't have any configuration */ - if (!dev->chip_info) { - return; - } - /* The programmer is responsible for ensuring - * a valid gpio configuration. - */ - - /* Get the chip configuration */ - config = dev->chip_info; - /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); - if (!res) { - return; - } - - /* Set the use selects */ - set_i3100_gpio_use_sel(dev, res, config); - - /* Set the IO direction */ - set_i3100_gpio_direction(dev, res, config); - - /* Setup the input inverters */ - set_i3100_gpio_inv(dev, res, config); - - /* Set the value on the GPIO output pins */ - set_i3100_gpio_level(dev, res, config); - -} - - -static void lpc_init(struct device *dev) -{ - struct resource *res; - - /* Enable IO APIC */ - res = find_resource(dev, RCBA); - if (!res) { - return; - } - *((u8 *)((u32)res->base + 0x31ff)) |= (1 << 0); - - // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode - // (register 0x10/0x11) while the old code used int 1 (register 0x12) - // ... Why? - setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IOAPIC ID - - /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */ - pci_write_config32(dev, 0xd0, 0x00000000); - - i3100_enable_serial_irqs(dev); - - /* Set up the PIRQ */ - i3100_pirq_init(dev); - - /* Setup power options */ - i3100_power_options(dev); - - /* Set the state of the gpio lines */ - i3100_gpio_init(dev); - - /* Initialize the real time clock */ - cmos_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - setup_i8259(); - i8259_configure_irq_trigger(9, 1); -} - -static void i3100_lpc_read_resources(device_t dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); - - /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); - - /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add resource for RCBA */ - res = new_resource(dev, RCBA); - res->size = 0x4000; - res->limit = 0xffffc000; - res->align = 14; - res->gran = 14; - res->flags = IORESOURCE_MEM; -} - -static void i3100_lpc_enable_resources(device_t dev) -{ - u8 acpi_cntl, gpio_cntl; - - /* Enable the normal pci resources */ - pci_dev_enable_resources(dev); - - /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 7); - pci_write_config8(dev, 0x44, acpi_cntl); - - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x4c); - gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x4c, gpio_cntl); - - /* Enable the RCBA */ - pci_write_config32(dev, RCBA, pci_read_config32(dev, RCBA) | (1 << 0)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations lpc_ops = { - .read_resources = i3100_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = i3100_lpc_enable_resources, - .init = lpc_init, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .scan_bus = scan_lpc_bus, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_LPC, -}; - -static const struct pci_driver lpc_driver_ep80579 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_LPC, -}; diff --git a/src/southbridge/intel/i3100/pci.c b/src/southbridge/intel/i3100/pci.c deleted file mode 100644 index 6ad0318cce..0000000000 --- a/src/southbridge/intel/i3100/pci.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - -static void pci_init(struct device *dev) -{ -} - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCI, -}; diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c deleted file mode 100644 index 3782f30e6d..0000000000 --- a/src/southbridge/intel/i3100/pciexp_portb.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pciexp.h> -#include <arch/io.h> -#include "chip.h" -#include <reset.h> - -#define PCIE_LCTL 0x50 -#define PCIE_LSTS 0x52 - -typedef struct northbridge_intel_i3100_config config_t; - -static void pcie_init(struct device *dev) -{ -} - -static void pcie_scan_bridge(struct device *dev) -{ - u16 val; - u16 ctl; - int flag = 0; - do { - val = pci_read_config16(dev, PCIE_LSTS); - printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val); - if ((val & (1<<10)) && (!flag)) { /* training error */ - ctl = pci_read_config16(dev, PCIE_LCTL); - pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5))); - val = pci_read_config16(dev, PCIE_LSTS); - printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val); - flag=1; - hard_reset(); - } - } while (val & (3<<10)); - - pciexp_scan_bridge(dev); -} - -static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0, -}; - -static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1, -}; - -static const struct pci_driver pci_driver_2 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2, -}; - -static const struct pci_driver pci_driver_3 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3, -}; diff --git a/src/southbridge/intel/i3100/reset.c b/src/southbridge/intel/i3100/reset.c deleted file mode 100644 index af000e3e66..0000000000 --- a/src/southbridge/intel/i3100/reset.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <arch/io.h> -#include <reset.h> - -void do_hard_reset(void) -{ - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c deleted file mode 100644 index 27bd2ce141..0000000000 --- a/src/southbridge/intel/i3100/sata.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/* This code is based on src/southbridge/intel/esb6300/esb6300_sata.c */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - -typedef struct southbridge_intel_i3100_config config_t; - -static void sata_init(struct device *dev) -{ - u8 ahci; - u32 *ahci_bar; - config_t *config = dev->chip_info; - - if (config == NULL) { - printk(BIOS_ERR, "i3100_sata: error: device not in devicetree.cb!\n"); - return; - } - - /* Get the chip configuration */ - ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03; - - /* Enable SATA devices */ - printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); - - if (ahci) { - /* AHCI mode */ - pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0)); - - /* Enable ports */ - pci_write_config8(dev, SATA_PCS, 0x03); - pci_write_config8(dev, SATA_PCS + 1, 0x0F); - - /* Setup timings */ - pci_write_config16(dev, SATA_PTIM, 0x8000); - pci_write_config16(dev, SATA_STIM, 0x8000); - - /* Synchronous DMA */ - pci_write_config8(dev, SATA_SYNCC, 0); - pci_write_config16(dev, SATA_SYNCTIM, 0); - - /* IDE I/O configuration */ - pci_write_config32(dev, SATA_IIOC, 0); - - ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); - ahci_bar[3] = config->sata_ports_implemented; - } else { - /* SATA configuration */ - pci_write_config8(dev, SATA_CMD, 0x07); - pci_write_config8(dev, SATA_PI, 0x8f); - - /* Set timings */ - pci_write_config16(dev, SATA_PTIM, 0x0a307); - pci_write_config16(dev, SATA_STIM, 0x0a307); - - /* Sync DMA */ - pci_write_config8(dev, SATA_SYNCC, 0x0f); - pci_write_config16(dev, SATA_SYNCTIM, 0x1111); - - /* Fast ATA */ - pci_write_config16(dev, SATA_IIOC, 0x1000); - - /* Select IDE mode */ - pci_write_config8(dev, SATA_MAP, 0x00); - - /* Enable ports 0-3 */ - pci_write_config8(dev, SATA_PCS + 1, 0x0f); - - } - - /* secret init sequence, required */ - pci_write_config32(dev, 0x94, 0x00400180); - pci_write_config32(dev, 0xa0, 0x18); - pci_write_config32(dev, 0xa4, 0x224); - pci_write_config32(dev, 0xa0, 0x42); - pci_write_config32(dev, 0xa4, 0x22006d); - pci_write_config32(dev, 0xa0, 0x84); - pci_write_config32(dev, 0xa4, 0x24); - pci_write_config32(dev, 0xa0, 0x7a); - pci_write_config32(dev, 0xa4, 0x220000); - pci_write_config32(dev, 0xa0, 0x9c); - pci_write_config32(dev, 0xa4, 0x24); - pci_write_config32(dev, 0xa0, 0x90); - pci_write_config32(dev, 0xa4, 0x220000); - pci_write_config32(dev, 0xa0, 0xa0); - pci_write_config32(dev, 0xa4, 0x12492aa); - - printk(BIOS_DEBUG, "SATA Enabled\n"); -} - -static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = sata_set_subsystem, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_IDE, -}; - -static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_AHCI, -}; - -static const struct pci_driver ide_driver_ep80579 __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_IDE, -}; - -static const struct pci_driver sata_driver_ep80579 __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI, -}; diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c deleted file mode 100644 index 850982adc5..0000000000 --- a/src/southbridge/intel/i3100/smbus.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <device/device.h> -#include <device/path.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/smbus.h> -#include <arch/io.h> -#include <southbridge/intel/common/smbus.h> -#include "i3100.h" - -static int lsmbus_read_byte(device_t dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(device_t dev, u8 address, u8 byte) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20); - - return do_smbus_write_byte(res->base, device, address, byte); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &smbus_set_subsystem, -}; - -static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_smbus, - .enable = i3100_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; - -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_SMB, -}; - -static const struct pci_driver smbus_driver_ep80579 __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_SMB, -}; diff --git a/src/southbridge/intel/i3100/uhci.c b/src/southbridge/intel/i3100/uhci.c deleted file mode 100644 index befde9228c..0000000000 --- a/src/southbridge/intel/i3100/uhci.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include "i3100.h" - -static void uhci_init(struct device *dev) -{ -} - -static void uhci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - -static struct pci_operations lops_pci = { - .set_subsystem = &uhci_set_subsystem, -}; - -static struct device_operations uhci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = uhci_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver uhci_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_UHCI, -}; - -static const struct pci_driver usb2_driver __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_3100_UHCI2, -}; - -static const struct pci_driver uhci_driver_ep80579 __pci_driver = { - .ops = &uhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_EP80579_UHCI, -}; diff --git a/src/superio/intel/i3100/Kconfig b/src/superio/intel/i3100/Kconfig deleted file mode 100644 index e797bd7dfa..0000000000 --- a/src/superio/intel/i3100/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SUPERIO_INTEL_I3100 - bool diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc deleted file mode 100644 index 840483d9c9..0000000000 --- a/src/superio/intel/i3100/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Arastra, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c -ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c deleted file mode 100644 index 0b0bb26825..0000000000 --- a/src/superio/intel/i3100/early_serial.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include <stdint.h> -#include "i3100.h" - -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x80, port); - outb(0x86, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - - outb(0x68, port); - outb(0x08, port); -} - -/* Enable device interrupts, set UART_CLK predivide. */ -void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) -{ - pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); - pnp_exit_ext_func_mode(dev); -} - -void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h deleted file mode 100644 index fa71c058eb..0000000000 --- a/src/superio/intel/i3100/i3100.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_INTEL_I3100_H -#define SUPERIO_INTEL_I3100_H - -/* - * Datasheet: - * - Name: Intel 3100 Chipset - * - URL: http://www.intel.com/design/intarch/datashts/313458.htm - * - PDF: http://download.intel.com/design/intarch/datashts/31345803.pdf - * - Revision / Date: 007, October 2008 - * - Order number: 313458-007US - */ - -/* - * The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is - * very similar to a Super I/O, both in functionality and config mechanism. - * - * The SIW contains: - * - UART(s) - * - Serial interrupt controller - * - Watchdog timer (WDT) - * - LPC interface - */ - -/* Logical device numbers (LDNs). */ -#define I3100_SP1 0x04 /* Com1 */ -#define I3100_SP2 0x05 /* Com2 */ -#define I3100_WDT 0x06 /* Watchdog timer */ - -/* Registers and bit definitions: */ - -#define I3100_SIW_CONFIGURATION 0x29 - -/* - * SIW_CONFIGURATION[3:2] = UART_CLK predivide - * 00: divide by 1 - * 01: divide by 8 - * 10: divide by 26 - * 11: reserved - */ -#define I3100_UART_CLK_PREDIVIDE_1 0x00 -#define I3100_UART_CLK_PREDIVIDE_8 0x01 -#define I3100_UART_CLK_PREDIVIDE_26 0x02 - -#include <arch/io.h> -#include <stdint.h> - -void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide); -void i3100_enable_serial(pnp_devfn_t dev, u16 iobase); - -#endif /* SUPERIO_INTEL_I3100_H */ diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c deleted file mode 100644 index 1055b7af72..0000000000 --- a/src/superio/intel/i3100/superio.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> -#include <device/device.h> -#include <device/pnp.h> -#include "i3100.h" -#include <arch/io.h> - -static void pnp_enter_ext_func_mode(struct device *dev) -{ - outb(0x80, dev->path.pnp.port); - outb(0x86, dev->path.pnp.port); -} - -static void pnp_exit_ext_func_mode(struct device *dev) -{ - outb(0x68, dev->path.pnp.port); - outb(0x08, dev->path.pnp.port); -} - -static void i3100_init(struct device *dev) -{ - if (!dev->enabled) - return; -} - -static const struct pnp_mode_ops pnp_conf_mode_ops = { - .enter_conf_mode = pnp_enter_ext_func_mode, - .exit_conf_mode = pnp_exit_ext_func_mode, -}; - -static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = i3100_init, - .ops_pnp_mode = &pnp_conf_mode_ops, -}; - -static struct pnp_info pnp_dev_info[] = { - { &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, - { &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, -}; - -static void enable_dev(struct device *dev) -{ - pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); -} - -struct chip_operations superio_intel_i3100_ops = { - CHIP_NAME("Intel 3100 Super I/O") - .enable_dev = enable_dev, -}; |