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-rw-r--r--src/Kconfig1
-rw-r--r--src/console/Kconfig8
-rw-r--r--src/console/console.c3
-rw-r--r--src/drivers/spi/Kconfig4
-rw-r--r--src/drivers/spi/Makefile.inc5
-rw-r--r--src/drivers/spi/spiconsole.c71
-rw-r--r--src/include/console/spi.h72
-rw-r--r--src/soc/intel/baytrail/Kconfig1
-rw-r--r--src/soc/intel/braswell/Kconfig1
-rw-r--r--src/soc/intel/broadwell/Kconfig1
-rw-r--r--src/soc/intel/fsp_baytrail/Kconfig1
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig1
12 files changed, 169 insertions, 0 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 902855ec8d..bab05f286a 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -777,6 +777,7 @@ config DEBUG_SMI
bool "Output verbose SMI debug messages"
default n
depends on HAVE_SMI_HANDLER
+ select SPI_FLASH_SMM if SPI_CONSOLE
help
This option enables additional SMI related debug messages.
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 7d6fa0e36f..a2f893a6fc 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -211,6 +211,14 @@ config CONSOLE_QEMU_DEBUGCON_PORT
depends on CONSOLE_QEMU_DEBUGCON
default 0x402
+config SPI_CONSOLE
+ bool "SPI debug console output"
+ depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH
+ help
+ Enable support for the debug console on the Dediprog EM100Pro.
+ This is currently working only in ramstage due to how the spi
+ drivers are written.
+
choice
prompt "Default console log level"
default DEFAULT_CONSOLE_LOGLEVEL_8
diff --git a/src/console/console.c b/src/console/console.c
index 00c0f1ce2e..855de648cd 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -24,6 +24,7 @@
#include <console/streams.h>
#include <console/uart.h>
#include <console/usb.h>
+#include <console/spi.h>
#include <rules.h>
void console_hw_init(void)
@@ -35,6 +36,7 @@ void console_hw_init(void)
__uart_init();
__ne2k_init();
__usbdebug_init();
+ __spiconsole_init();
}
void console_tx_byte(unsigned char byte)
@@ -54,6 +56,7 @@ void console_tx_byte(unsigned char byte)
__uart_tx_byte(byte);
__ne2k_tx_byte(byte);
__usb_tx_byte(byte);
+ __spiconsole_tx_byte(byte);
}
void console_tx_flush(void)
diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig
index 4052bb4713..dedb88f664 100644
--- a/src/drivers/spi/Kconfig
+++ b/src/drivers/spi/Kconfig
@@ -137,3 +137,7 @@ config SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
to the chip on MOSI and data is received on both MOSI and MISO.
endif # SPI_FLASH
+
+config HAVE_SPI_CONSOLE_SUPPORT
+ def_bool n
+
diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc
index ade34a2988..6697c702fb 100644
--- a/src/drivers/spi/Makefile.inc
+++ b/src/drivers/spi/Makefile.inc
@@ -1,5 +1,10 @@
# SPI flash driver interface
+ifeq ($(CONFIG_SPI_CONSOLE),y)
+ramstage-y += spiconsole.c
+smm-$(CONFIG_DEBUG_SMI) += spiconsole.c
+endif
+
ifeq ($(CONFIG_COMMON_CBFS_SPI_WRAPPER),y)
bootblock-y += spi_flash.c
bootblock-$(CONFIG_SPI_FLASH_EON) += eon.c
diff --git a/src/drivers/spi/spiconsole.c b/src/drivers/spi/spiconsole.c
new file mode 100644
index 0000000000..39a574c3ca
--- /dev/null
+++ b/src/drivers/spi/spiconsole.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <spi-generic.h>
+#include <spi_flash.h>
+#include <console/spi.h>
+
+void spiconsole_init(void) {
+ spi_init();
+ return;
+}
+
+/*
+ * The EM100 'hyper terminal' specification defines a header of 9 characters.
+ * Because of this, devices with a spi_crop_chunk of less than 10 characters
+ * can't be supported by this standard.
+ *
+ * To add support in romstage, the static struct here and the ones used by
+ * spi_xfer will need to be modified - removed, or mapped into cbmem.
+ *
+ * Because the Dediprog software expects strings, not single characters, and
+ * because of the header overhead, this builds up a buffer to send.
+ */
+void spiconsole_tx_byte(unsigned char c) {
+ static struct em100_msg msg = {
+ .header.spi_command = EM100_DEDICATED_CMD,
+ .header.em100_command = EM100_UFIFO_CMD,
+ .header.msg_signature = EM100_MSG_SIGNATURE,
+ .header.msg_type = EM100_MSG_ASCII,
+ .header.msg_length = 0
+ };
+
+ /* Verify the spi buffer is big enough to send even a single byte */
+ if (spi_crop_chunk(0,MAX_MSG_LENGTH) <
+ sizeof(struct em100_msg_header) + 1)
+ return;
+
+ msg.data[msg.header.msg_length] = c;
+ msg.header.msg_length++;
+
+ /* Send the data on newline or when the max spi length is reached */
+ if (c == '\n' || (sizeof(struct em100_msg_header) +
+ msg.header.msg_length == spi_crop_chunk(0,
+ MAX_MSG_LENGTH))) {
+ struct spi_slave spi = {.rw = SPI_READ_FLAG};
+
+ spi_xfer(&spi, &msg, sizeof(struct em100_msg_header) +
+ msg.header.msg_length, NULL, 0);
+
+ msg.header.msg_length = 0;
+ }
+
+ return;
+}
+
diff --git a/src/include/console/spi.h b/src/include/console/spi.h
new file mode 100644
index 0000000000..c47fec541a
--- /dev/null
+++ b/src/include/console/spi.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef CONSOLE_SPI_H
+#define CONSOLE_SPI_H 1
+
+#include <rules.h>
+#include <stdint.h>
+
+void spiconsole_init(void);
+void spiconsole_tx_byte(unsigned char c);
+
+#define __CONSOLE_SPI_ENABLE__ CONFIG_SPI_CONSOLE && \
+ (ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI))
+
+#if __CONSOLE_SPI_ENABLE__
+static inline void __spiconsole_init(void) { spiconsole_init(); }
+static inline void __spiconsole_tx_byte(u8 data) { spiconsole_tx_byte(data); }
+#else
+static inline void __spiconsole_init(void) {}
+static inline void __spiconsole_tx_byte(u8 data) {}
+#endif /* __CONSOLE_SPI_ENABLE__ */
+
+#define MAX_MSG_LENGTH 128
+
+#define EM100_DEDICATED_CMD 0x11
+#define EM100_UFIFO_CMD 0xC0
+#define EM100_MSG_SIGNATURE 0x47364440
+
+enum em100_message_types {
+ EM100_MSG_CHECKPOINT_1B = 0x01,
+ EM100_MSG_CHECKPOINT_2B,
+ EM100_MSG_CHECKPOINT_4B,
+ EM100_MSG_HEX,
+ EM100_MSG_ASCII,
+ EM100_MSG_TIMESTAMP,
+ EM100_MSG_LOOKUP
+};
+
+struct em100_msg_header {
+ uint8_t spi_command;
+ uint8_t reserved;
+ uint8_t em100_command;
+ uint32_t msg_signature;
+ uint8_t msg_type;
+ uint8_t msg_length;
+} __attribute__ ((packed));
+
+struct em100_msg {
+ struct em100_msg_header header;
+ char data[MAX_MSG_LENGTH];
+} __attribute__ ((packed));
+
+
+
+#endif /* CONSOLE_SPI_H */
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 921f568fa9..8de32de8f4 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select SOC_INTEL_COMMON
select HAVE_INTEL_FIRMWARE
+ select HAVE_SPI_CONSOLE_SUPPORT
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index f76b9b244c..5a41056103 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -49,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select USE_GENERIC_FSP_CAR_INC
select HAVE_INTEL_FIRMWARE
+ select HAVE_SPI_CONSOLE_SUPPORT
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 6561fe27fa..33644e840b 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON
select HAVE_INTEL_FIRMWARE
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select HAVE_SPI_CONSOLE_SUPPORT
config BOOTBLOCK_CPU_INIT
string
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 36229de7a2..d9114fc008 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_INTEL_FIRMWARE
+ select HAVE_SPI_CONSOLE_SUPPORT
config SOC_INTEL_FSP_BAYTRAIL_MD
bool
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 3c8ae115e5..3221cff278 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -33,6 +33,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
select HAVE_INTEL_FIRMWARE
+ select HAVE_SPI_CONSOLE_SUPPORT
config INTEL_LYNXPOINT_LP
bool