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-rw-r--r--src/soc/amd/picasso/romstage.c13
-rw-r--r--src/soc/amd/stoneyridge/romstage.c13
-rw-r--r--src/soc/intel/apollolake/memmap.c13
-rw-r--r--src/soc/intel/denverton_ns/memmap.c13
-rw-r--r--src/soc/intel/skylake/memmap.c13
5 files changed, 10 insertions, 55 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 4f18b42276..9882d9115e 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -44,8 +44,6 @@ asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();
console_init();
@@ -87,15 +85,8 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(&pcf);
post_code(0x45);
run_postcar_phase(&pcf);
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 0d65ef6c82..4032d3f8b8 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -85,8 +85,6 @@ asmlinkage void car_stage_entry(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
msr_t base, mask;
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@@ -172,15 +170,8 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(&pcf);
post_code(0x45);
run_postcar_phase(&pcf);
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index bda43bbdbf..905fa64571 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -53,8 +53,6 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this point exact
@@ -67,13 +65,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(pcf);
}
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index f7b2e07157..9f788ddb41 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -81,8 +81,6 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this point exact
@@ -93,13 +91,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
MTRR_TYPE_WRBACK);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(pcf);
}
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 4c3c58a12d..29f2517468 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -296,8 +296,6 @@ void *cbmem_top(void)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this
@@ -310,14 +308,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
+ /* Cache the TSEG region */
+ postcar_enable_tseg_cache(pcf);
}
#endif