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-rw-r--r--src/soc/amd/stoneyridge/acpi.c6
-rw-r--r--src/soc/amd/stoneyridge/include/soc/northbridge.h10
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h1
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c4
4 files changed, 16 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index d56e105607..1f6e62abb7 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -31,6 +31,7 @@
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
+#include <soc/northbridge.h>
#include <soc/nvs.h>
#include <soc/gpio.h>
@@ -237,11 +238,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
void generate_cpu_entries(struct device *device)
{
int cores, cpu;
- struct device *cdb_dev;
/* Stoney Ridge is single node, just report # of cores */
- cdb_dev = dev_find_slot(0, NB_DEVFN);
- cores = (pci_read_config32(cdb_dev, 0x84) & 0xff) + 1;
+ cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
+ cores++; /* number of cores is CmpCap+1 */
printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 7f7ac5d750..d62c791b09 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -62,9 +62,15 @@
# define MMIO_RE (1 << 0)
#define D18F1_MMIO_LIMIT0_LO 0x84
# define MMIO_NP (1 << 7)
+#define D18F1_IO_BASE0_LO 0xc0
+#define D18F1_IO_BASE1_LO 0xc8
+#define D18F1_IO_BASE2_LO 0xd0
+#define D18F1_IO_BASE3_LO 0xd8
+#define D18F1_MMIO_BASE7_LO 0xb8
#define D18F1_MMIO_BASELIM0_HI 0x180
#define D18F1_MMIO_BASE8_LO 0x1a0
#define D18F1_MMIO_LIMIT8_LO 0x1a4
+#define D18F1_MMIO_BASE11_LO 0x1b8
#define D18F1_MMIO_BASELIM8_HI 0x1c0
#define NB_MMIO_BASE_LO(reg) ((reg) * 2 * sizeof(uint32_t) + (((reg) < 8) \
? D18F1_MMIO_BASE0_LO \
@@ -89,6 +95,10 @@
#define D18F1_VGAEN 0xf4
# define VGA_ADDR_ENABLE (1 << 0)
+/* D18F5 */
+#define NB_CAPABILITIES2 0x84
+#define CMP_CAP_MASK 0xff
+
enum {
/* SMM handler area. */
SMM_SUBREGION_HANDLER,
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 681f14922a..cb9c4c6e7c 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -304,6 +304,7 @@
#define LPC_WIDEIO2_GENERIC_PORT 0x90
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
+#define SPI_BASE_RESERVED (BIT(4) | BIT(5))
#define ROUTE_TPM_2_SPI BIT(3)
#define SPI_ABORT_ENABLE BIT(2)
#define SPI_ROM_ENABLE BIT(1)
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 40e69dbbad..6157e5013b 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -414,8 +414,8 @@ static uintptr_t sb_spibase(void)
/* Make sure the base address is predictable */
base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
- enables = base & 0xf;
- base &= ~0x3f;
+ enables = base & SPI_PRESERVE_BITS;
+ base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED);
if (!base) {
base = SPI_BASE_ADDRESS;