diff options
| -rw-r--r-- | src/arch/armv7/lib/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/arch/armv7/lib/cache-cp15.c | 6 | ||||
| -rw-r--r-- | src/arch/armv7/stages.c | 16 | ||||
| -rw-r--r-- | src/cpu/armltd/cortex-a9/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5250/Makefile.inc | 2 |
5 files changed, 26 insertions, 2 deletions
diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 391b6a54b1..388864aa28 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c +bootblock-y += cache_v7.c +bootblock-y += cache-cp15.c romstage-y += cache_v7.c romstage-y += cache-cp15.c @@ -14,6 +16,7 @@ ramstage-y += div64.S #ramstage-y += memcpy.S #ramstage-y += memset.S ramstage-y += syslib.c +ramstage-y += cache_v7.c #FIXME(dhendrix): should this be a config option? romstage-y += eabi_compat.c diff --git a/src/arch/armv7/lib/cache-cp15.c b/src/arch/armv7/lib/cache-cp15.c index cfbdb941a0..e08ea57a56 100644 --- a/src/arch/armv7/lib/cache-cp15.c +++ b/src/arch/armv7/lib/cache-cp15.c @@ -46,8 +46,12 @@ static void set_section_dcache(int section, enum dcache_option option) /* * FIXME(dhendrix): This calculation is from arch/arm/lib/board.c * in u-boot. We may need to subtract more due to logging. + * FIXME(rminnich) + * The cast avoids an incorrect overflow diagnostic. + * We really need to start adding ULL to constants that are + * intrinsically unsigned. */ - tlb_addr = (CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20UL)); + tlb_addr = ((u32)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20UL)); tlb_addr -= tlb_size; /* round down to next 64KB limit */ tlb_addr &= ~(0x10000 - 1); diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c index 05b3e1d9ff..c37c1ddc23 100644 --- a/src/arch/armv7/stages.c +++ b/src/arch/armv7/stages.c @@ -32,14 +32,28 @@ */ #include <arch/stages.h> +#include <arch/armv7/include/common.h> void stage_entry(void) { main(); } +/* we had marked 'doit' as 'noreturn'. + * There is no apparent harm in leaving it as something we can return from, and in the one + * case where we call a payload, the payload is allowed to return. + * Hence, leave it as something we can return from. + */ void stage_exit(void *addr) { - __attribute__((noreturn)) void (*doit)(void) = addr; + void (*doit)(void) = addr; + /* make sure any code we installed is written to memory. Not all ARM have + * unified caches. + */ + flush_dcache_all(); + /* Because most stages copy code to memory, it's a safe and hygienic thing + * to flush the icache here. + */ + invalidate_icache_all(); doit(); } diff --git a/src/cpu/armltd/cortex-a9/Makefile.inc b/src/cpu/armltd/cortex-a9/Makefile.inc index d1e7edfdee..f1a3689691 100644 --- a/src/cpu/armltd/cortex-a9/Makefile.inc +++ b/src/cpu/armltd/cortex-a9/Makefile.inc @@ -1,2 +1,3 @@ ramstage-y += cache.c romstage-y += cache.c +bootblock-y += cache.c diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index c9a9341641..33fcedcc40 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,6 +9,7 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c +bootblock-y += exynos_cache.c romstage-y += clock.c romstage-y += clock_init.c @@ -28,6 +29,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += exynos_cache.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c |