diff options
| -rw-r--r-- | src/soc/mediatek/mt8173/dsi.c | 19 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/dsi.h | 26 |
2 files changed, 45 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index 1d195719b0..3500bf1d01 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -20,6 +20,7 @@ #include <soc/i2c.h> #include <soc/gpio.h> #include <soc/dsi.h> +#include <timer.h> static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, const struct edid *edid) @@ -298,3 +299,21 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, return 0; } + +void mtk_dsi_pin_drv_ctrl(void) +{ + struct stopwatch sw; + + setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); + + stopwatch_init_usecs_expire(&sw, 1000); + + do { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "enable lvdstx_power failed!!!\n"); + return; + } + } while ((read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK) == 0); + + clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); +} diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 1abbd78ae9..73f4425684 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -263,7 +263,33 @@ enum { RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) }; +/* LVDS_TX1_REG */ +struct lvds_tx1_regs { + u32 lvdstx1_ctl1; + u32 lvdstx1_ctl2; + u32 lvdstx1_ctl3; + u32 lvdstx1_ctl4; + u32 lvdstx1_ctl5; + u32 vopll_ctl1; + u32 vopll_ctl2; + u32 vopll_ctl3; +}; + +static struct lvds_tx1_regs * const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800); + +/* LVDS_VOPLL_CTRL3 */ +enum { + RG_LVDSTX_21EDG = BIT(0), + RG_LVDSTX_21LEV = BIT(1), + RG_LVDSTX_51EDG = BIT(2), + RG_LVDSTX_51LEV = BIT(3), + RG_AD_LVDSTX_PWR_ACK = BIT(4), + RG_DA_LVDS_ISO_EN = BIT(8), + RG_DA_LVDSTX_PWR_ON = BIT(9) +}; + int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes, const struct edid *edid); +void mtk_dsi_pin_drv_ctrl(void); #endif |