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-rw-r--r--src/drivers/uart/sifive.c15
-rw-r--r--src/soc/sifive/fu540/Kconfig2
-rw-r--r--src/soc/sifive/fu540/uart.c8
3 files changed, 20 insertions, 5 deletions
diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c
index dd47cafcf1..ce8ead0d05 100644
--- a/src/drivers/uart/sifive.c
+++ b/src/drivers/uart/sifive.c
@@ -46,11 +46,10 @@ struct sifive_uart_registers {
#define IP_TXWM BIT(0)
#define IP_RXWM BIT(1)
-void uart_init(int idx)
+static void sifive_uart_init(struct sifive_uart_registers *regs, int div)
{
- struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
-
- /* TODO: Configure the divisor */
+ /* Configure the divisor */
+ write32(&regs->div, div);
/* Enable transmission, one stop bit, transmit watermark at 1 */
write32(&regs->txctrl, TXCTRL_TXEN|TXCTRL_NSTOP(1)|TXCTRL_TXCNT(1));
@@ -59,6 +58,14 @@ void uart_init(int idx)
write32(&regs->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0));
}
+void uart_init(int idx)
+{
+ unsigned int div;
+ div = uart_baudrate_divisor(get_uart_baudrate(),
+ uart_platform_refclk(), uart_input_clock_divider());
+ sifive_uart_init(uart_platform_baseptr(idx), div);
+}
+
static bool uart_can_tx(struct sifive_uart_registers *regs)
{
return !(read32(&regs->txdata) & TXDATA_FULL);
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index c438a10162..457d16bb4e 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -20,7 +20,7 @@ config SOC_SIFIVE_FU540
select ARCH_RAMSTAGE_RISCV
select BOOTBLOCK_CONSOLE
select DRIVERS_UART_SIFIVE
-
+ select UART_OVERRIDE_REFCLK
if SOC_SIFIVE_FU540
config RISCV_ARCH
diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c
index 940dc97856..c53f42d9d8 100644
--- a/src/soc/sifive/fu540/uart.c
+++ b/src/soc/sifive/fu540/uart.c
@@ -23,3 +23,11 @@ uintptr_t uart_platform_base(int idx)
else
return 0;
}
+
+unsigned int uart_platform_refclk(void)
+{
+ /*
+ * The SiFive UART uses tlclk, which is coreclk/2 as input
+ */
+ return 33330000 / 2;
+}