diff options
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 17 | ||||
| -rw-r--r-- | src/soc/amd/picasso/chip.c | 21 | ||||
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 36 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/cpu.h | 10 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/northbridge.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/picasso/northbridge.c | 147 | ||||
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 117 | ||||
| -rw-r--r-- | src/soc/amd/picasso/southbridge.c | 56 |
9 files changed, 7 insertions, 403 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 33aae2655f..a930f60d27 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,8 +49,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA - select SOC_AMD_COMMON_BLOCK_PI - select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 select C_ENVIRONMENT_BOOTBLOCK select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH @@ -106,18 +104,6 @@ config CPU_ADDR_BITS int default 48 -config BOTTOMIO_POSITION - hex "Bottom of 32-bit IO space" - default 0xD0000000 - help - If PCI peripherals with big BARs are connected to the system - the bottom of the IO must be decreased to allocate such - devices. - - Declare the beginning of the 128MB-aligned MMIO region. This - option is useful when PCI peripherals requesting large address - ranges are present. - config MMCONF_BASE_ADDRESS hex default 0xF8000000 @@ -199,7 +185,7 @@ config PICASSO_LEGACY_FREE bool "System is legacy free" help Select y if there is no keyboard controller in the system. - This sets variables in AGESA and ACPI. + This sets a variable in ACPI. config SERIRQ_CONTINUOUS_MODE bool @@ -213,7 +199,6 @@ config PICASSO_ACPI_IO_BASE default 0x400 help Base address for the ACPI registers. - This value must match the hardcoded value of AGESA. config PICASSO_UART bool "UART controller on Picasso" diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index b9e98c538c..65d98b127d 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -25,9 +25,6 @@ #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> - #include "chip.h" /* Supplied by i2c.c */ @@ -113,7 +110,6 @@ const char *soc_acpi_name(const struct device *dev) struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = soc_acpi_name, }; @@ -141,7 +137,6 @@ static void soc_init(void *chip_info) static void soc_final(void *chip_info) { southbridge_final(chip_info); - fam15_finalize(chip_info); } struct chip_operations soc_amd_picasso_ops = { @@ -150,19 +145,3 @@ struct chip_operations soc_amd_picasso_ops = { .init = soc_init, .final = soc_final }; - -static void earliest_ramstage(void *unused) -{ - int s3_resume = acpi_s3_resume_allowed() && - romstage_handoff_is_resume(); - if (!s3_resume) { - post_code(0x47); - do_agesawrapper(AMD_INIT_ENV, "amdinitenv"); - } else { - /* Complete the initial system restoration */ - post_code(0x46); - do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore"); - } -} - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL); diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index ff9c845898..39c70269da 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -23,33 +23,9 @@ #include <soc/i2c.h> #include <arch/acpi_device.h> -#define MAX_NODES 1 -#define MAX_DRAM_CH 1 -#define MAX_DIMMS_PER_CH 2 - #define PICASSO_I2C_DEV_MAX 4 struct soc_amd_picasso_config { - u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; - enum { - DRAM_CONTENTS_KEEP, - DRAM_CONTENTS_CLEAR - } dram_clear_on_reset; - - enum { - /* Do not enable UMA in the system. */ - UMAMODE_NONE, - /* Enable UMA with a specific size. */ - UMAMODE_SPECIFIED_SIZE, - /* Let AGESA determine the proper size. Non-legacy requires - * the resolution to be specified PLATFORM_CONFIGURATION */ - UMAMODE_AUTO_LEGACY, - UMAMODE_AUTO_NON_LEGACY, - } uma_mode; - - /* Used if UMAMODE_SPECIFIED_SIZE is set. */ - size_t uma_size; - /* * If sb_reset_i2c_slaves() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. @@ -60,18 +36,6 @@ struct soc_amd_picasso_config { */ u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; - u8 stapm_percent; - u32 stapm_time_ms; - u32 stapm_power_mw; - /* - * This specifies the LVDS/eDP power-up sequence time for the delay - * between VaryBL and BLON. - * 0 - Use the VBIOS default (default). The video BIOS default is 32ms. - * n - Values other than zero specify a setting of (4 * n) milliseconds - * time delay. - */ - u8 lvds_poseq_varybl_to_blon; - u8 lvds_poseq_blon_to_varybl; }; typedef struct soc_amd_picasso_config config_t; diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 7d4764567a..7bc1810dba 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,16 +18,8 @@ #include <device/device.h> -/* - * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest - * numbered registers. Any values defined below are subtracted from the - * highest numbered registers. - * - * todo: Revisit this once AGESA no longer programs MTRRs. - */ #define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_CAR_HEAP 2 -#define SOC_EARLY_VMTRR_TEMPRAM 3 +#define SOC_EARLY_VMTRR_TEMPRAM 2 void picasso_init_cpus(struct device *dev); void check_mca(void); diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index f7df2772c5..65705b93f3 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -110,6 +110,8 @@ enum { SMM_SUBREGION_NUM, }; +void amd_initcpuio(void); + /* * Fills in the arguments for the entire SMM region covered by chipset * protections. e.g. TSEG. diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index b28522e60f..565ab3084d 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -322,7 +322,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** - * @brief Save the UMA bize returned by AGESA + * @brief Save the UMA bize * * @param size = in bytes * @@ -330,7 +330,7 @@ void bootblock_fch_init(void); */ void save_uma_size(uint32_t size); /** - * @brief Save the UMA base address returned by AGESA + * @brief Save the UMA base address * * @param base = 64bit base address * diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 5985832c81..627ce03833 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -27,9 +27,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <romstage_handoff.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> -#include <agesa_headers.h> #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/southbridge.h> @@ -188,26 +185,6 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -static unsigned long acpi_fill_hest(acpi_hest_t *hest) -{ - void *addr, *current; - - /* Skip the HEST header. */ - current = (void *)(hest + 1); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, - (void *)((u32)addr + 2), *(uint16_t *)addr - 2); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, - (void *)((u32)addr + 2), *(uint16_t *)addr - 2); - - return (unsigned long)current; -} - static void northbridge_fill_ssdt_generator(struct device *device) { msr_t msr; @@ -233,106 +210,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device, unsigned long current, acpi_rsdp_t *rsdp) { - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *alib; - acpi_header_t *ivrs; - acpi_hest_t *hest; - acpi_bert_t *bert; - - /* HEST */ - current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; - acpi_write_hest(hest, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += hest->header.length; - - /* BERT */ - if (CONFIG(ACPI_BERT) && bert_errors_present()) { - /* Skip the table if no errors are present. ACPI driver reports - * a table with a 0-length region: - * BERT: [Firmware Bug]: table invalid. - */ - void *rgn; - size_t size; - bert_errors_region(&rgn, &size); - if (!rgn) { - printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); - } else { - current = ALIGN(current, 8); - bert = (acpi_bert_t *)current; - acpi_write_bert(bert, (uintptr_t)rgn, size); - acpi_add_table(rsdp, (void *)current); - current += bert->header.length; - } - } - - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = agesawrapper_getlateinitptr(PICK_IVRS); - if (ivrs != NULL) { - memcpy((void *)current, ivrs, ivrs->length); - ivrs = (acpi_header_t *)current; - current += ivrs->length; - acpi_add_table(rsdp, ivrs); - } else { - printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); - } - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *)current; - current += srat->header.length; - acpi_add_table(rsdp, srat); - } else { - printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); - } - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *)current; - current += slit->header.length; - acpi_add_table(rsdp, slit); - } else { - printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); - } - - /* ALIB */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); - alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); - if (alib != NULL) { - memcpy((void *)current, alib, alib->length); - alib = (acpi_header_t *)current; - current += alib->length; - acpi_add_table(rsdp, (void *)alib); - } else { - printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." - " Skipping.\n"); - } - - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); - if (ssdt != NULL) { - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *)current; - current += ssdt->length; - } else { - printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); - } - acpi_add_table(rsdp, ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + /* TODO - different mechanism to collect this info for Family 17h */ return current; } @@ -399,13 +277,6 @@ void fam15_finalize(void *chip_info) pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); } -void domain_enable_resources(struct device *dev) -{ - /* Must be called after PCI enumeration and resource allocation */ - if (!romstage_handoff_is_resume()) - do_agesawrapper(AMD_INIT_MID, "amdinitmid"); -} - void domain_set_resources(struct device *dev) { uint64_t uma_base = get_uma_base(); @@ -474,19 +345,3 @@ u32 map_oprom_vendev(u32 vendev) return new_vendev; } - -__weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } - -void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) -{ - const struct device *dev = SOC_IOMMU_DEV; - params->IommuSupport = dev && dev->enabled; - set_board_env_params(params); -} - -void SetNbMidParams(GNB_MID_CONFIGURATION *params) -{ - /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ - params->iGpuVgaMode = 0; - params->GnbIoapicAddress = IO_APIC2_ADDR; -} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 904f556202..950b41f5a3 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -27,8 +27,6 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <elog.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> #include <soc/northbridge.h> #include <soc/romstage.h> #include <soc/southbridge.h> @@ -40,22 +38,6 @@ void __weak mainboard_romstage_entry(int s3_resume) /* By default, don't do anything */ } -static void agesa_call(void) -{ - post_code(0x37); - do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); - - post_code(0x38); - /* APs will not exit amdinitearly */ - do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); -} - -static void bsp_agesa_call(void) -{ - set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ - agesa_call(); -} - asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -63,58 +45,20 @@ asmlinkage void car_stage_entry(void) void *smm_base; size_t smm_size; uintptr_t tseg_base; - msr_t base, mask; - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); - int i; console_init(); mainboard_romstage_entry(s3_resume); - bsp_agesa_call(); - if (!s3_resume) { post_code(0x40); - do_agesawrapper(AMD_INIT_POST, "amdinitpost"); - - post_code(0x41); - /* - * TODO: This is a hack to work around current AGESA behavior. - * AGESA needs to change to reflect that coreboot owns - * the MTRRs. - * - * After setting up DRAM, AGESA also completes the configuration - * of the MTRRs, setting regions to WB. Anything written to - * memory between now and and when CAR is dismantled will be - * in cache and lost. For now, set the regions UC to ensure - * the writes get to DRAM. - */ - for (i = 0 ; i < vmtrrs ; i++) { - base = rdmsr(MTRR_PHYS_BASE(i)); - mask = rdmsr(MTRR_PHYS_MASK(i)); - if (!(mask.lo & MTRR_PHYS_MASK_VALID)) - continue; - if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { - base.lo &= ~0x7; - base.lo |= MTRR_TYPE_UNCACHEABLE; - wrmsr(MTRR_PHYS_BASE(i), base); - } - } - /* Disable WB from to region 4GB-TOM2. */ - msr_t sys_cfg = rdmsr(SYSCFG_MSR); - sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; - wrmsr(SYSCFG_MSR, sys_cfg); if (CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); - - post_code(0x61); } post_code(0x43); @@ -155,64 +99,3 @@ asmlinkage void car_stage_entry(void) post_code(0x50); /* Should never see this post code. */ } - -void SetMemParams(AMD_POST_PARAMS *PostParams) -{ - const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n"); - /* In case of a BIOS error, only attempt to set UMA. */ - PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? - UMA_AUTO : UMA_NONE; - return; - } - - cfg = dev->chip_info; - - PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; - - switch (cfg->uma_mode) { - case UMAMODE_NONE: - PostParams->MemConfig.UmaMode = UMA_NONE; - break; - case UMAMODE_SPECIFIED_SIZE: - PostParams->MemConfig.UmaMode = UMA_SPECIFIED; - /* 64 KiB blocks. */ - PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); - break; - case UMAMODE_AUTO_LEGACY: - PostParams->MemConfig.UmaMode = UMA_AUTO; - PostParams->MemConfig.UmaVersion = UMA_LEGACY; - break; - case UMAMODE_AUTO_NON_LEGACY: - PostParams->MemConfig.UmaMode = UMA_AUTO; - PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; - break; - } -} - -void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) -{ - const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - struct _PLATFORM_CONFIGURATION *platform; - - if (!dev || !dev->chip_info) { - printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" - " config, STAPM unchanged\n"); - return; - } - cfg = dev->chip_info; - platform = &InitEarly->PlatformConfig; - if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && - (cfg->stapm_power_mw)) { - platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; - platform->PlatStapmConfig.CfgStapmTimeConstant = - cfg->stapm_time_ms; - platform->PkgPwrLimitDC = cfg->stapm_power_mw; - platform->PkgPwrLimitAC = cfg->stapm_power_mw; - platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; - } -} diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 87b933e119..84c15a7595 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -23,7 +23,6 @@ #include <device/pci_ops.h> #include <cbmem.h> #include <amdblocks/amd_pci_util.h> -#include <amdblocks/agesawrapper.h> #include <amdblocks/reset.h> #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> @@ -34,7 +33,6 @@ #include <soc/amd_pci_int_defs.h> #include <delay.h> #include <soc/pci_devs.h> -#include <agesa_headers.h> #include <soc/nvs.h> #include <types.h> @@ -54,60 +52,6 @@ const static struct picasso_aoac aoac_devs[] = { { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } }; -static int is_sata_config(void) -{ - return !((SataNativeIde == CONFIG_PICASSO_SATA_MODE) - || (SataLegacyIde == CONFIG_PICASSO_SATA_MODE)); -} - -static inline int sb_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || - (SataAhci == CONFIG_PICASSO_SATA_MODE); -} - -static inline int sb_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (SataNativeIde == CONFIG_PICASSO_SATA_MODE) || - (SataLegacyIde == CONFIG_PICASSO_SATA_MODE); -} - -void SetFchResetParams(FCH_RESET_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - if (dev && dev->enabled) { - params->SataEnable = sb_sata_enable(); - params->IdeEnable = sb_ide_enable(); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - } -} - -void SetFchEnvParams(FCH_INTERFACE *params) -{ - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - params->AzaliaController = AzEnable; - params->SataClass = CONFIG_PICASSO_SATA_MODE; - if (dev && dev->enabled) { - params->SataEnable = is_sata_config(); - params->IdeEnable = !params->SataEnable; - params->SataIdeMode = (CONFIG_PICASSO_SATA_MODE == - SataLegacyIde); - } else { - params->SataEnable = FALSE; - params->IdeEnable = FALSE; - params->SataIdeMode = FALSE; - } -} - -void SetFchMidParams(FCH_INTERFACE *params) -{ - SetFchEnvParams(params); -} - /* * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME * provides a visible association with the index, therefore helping |