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-rw-r--r--src/mainboard/asrock/b85m_pro4/Kconfig1
-rw-r--r--src/mainboard/asrock/b85m_pro4/bootblock.c10
2 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig
index 7098f9428e..20ff9b1fcb 100644
--- a/src/mainboard/asrock/b85m_pro4/Kconfig
+++ b/src/mainboard/asrock/b85m_pro4/Kconfig
@@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SUPERIO_NUVOTON_NCT6776
- select SUPERIO_NUVOTON_NCT6776_COM_A
config MAINBOARD_DIR
string
diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c
index f95fb52972..9b3746c521 100644
--- a/src/mainboard/asrock/b85m_pro4/bootblock.c
+++ b/src/mainboard/asrock/b85m_pro4/bootblock.c
@@ -13,9 +13,13 @@ void mainboard_config_superio(void)
{
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
- /* Select HWM/LED functions instead of floppy functions */
- pnp_write_config(GLOBAL_DEV, 0x1c, 0x03);
- pnp_write_config(GLOBAL_DEV, 0x24, 0x24);
+ /* Select SIO pin mux states */
+ pnp_write_config(GLOBAL_DEV, 0x1b, 0x68);
+ pnp_write_config(GLOBAL_DEV, 0x1c, 0x80);
+ pnp_write_config(GLOBAL_DEV, 0x24, 0x1c);
+ pnp_write_config(GLOBAL_DEV, 0x27, 0xd0);
+ pnp_write_config(GLOBAL_DEV, 0x2a, 0x62);
+ pnp_write_config(GLOBAL_DEV, 0x2f, 0x03);
/* Power RAM in S3 and let the PCH handle power failure actions */
pnp_set_logical_device(ACPI_DEV);