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-rw-r--r--src/mainboard/dell/s1850/Kconfig4
-rw-r--r--src/mainboard/dell/s1850/romstage.c3
-rw-r--r--src/mainboard/intel/jarrell/Kconfig4
-rw-r--r--src/mainboard/intel/jarrell/romstage.c2
-rw-r--r--src/northbridge/intel/e7520/Kconfig6
-rw-r--r--src/northbridge/intel/e7520/raminit.c6
-rw-r--r--src/northbridge/intel/e7525/Kconfig6
-rw-r--r--src/northbridge/intel/e7525/raminit.c6
-rw-r--r--src/northbridge/intel/i3100/Kconfig6
-rw-r--r--src/northbridge/intel/i3100/raminit.c6
10 files changed, 29 insertions, 20 deletions
diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig
index 22cdf7ed5b..4185dfcb9c 100644
--- a/src/mainboard/dell/s1850/Kconfig
+++ b/src/mainboard/dell/s1850/Kconfig
@@ -46,4 +46,8 @@ config IRQ_SLOT_COUNT
int
default 9
+config DIMM_MAP_LOGICAL
+ hex
+ default 0x2841
+
endif # BOARD_DELL_S1850
diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c
index 6ebf88cb0b..a935ffc13d 100644
--- a/src/mainboard/dell/s1850/romstage.c
+++ b/src/mainboard/dell/s1850/romstage.c
@@ -37,9 +37,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-/* this is very highly mainboard dependent, related to wiring */
-/* from factory BIOS via lspci */
-#define DIMM_MAP_LOGICAL 0x2841
#include "northbridge/intel/e7520/raminit.c"
#include "lib/generic_sdram.c"
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig
index f6c701d485..2ac8ea3c13 100644
--- a/src/mainboard/intel/jarrell/Kconfig
+++ b/src/mainboard/intel/jarrell/Kconfig
@@ -43,4 +43,8 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x1079
+config DIMM_MAP_LOGICAL
+ hex
+ default 0x0124
+
endif # BOARD_INTEL_JARRELL
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 0220ec8fab..530c22ae24 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -29,8 +29,6 @@
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-#define DIMM_MAP_LOGICAL 0x0124
-
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
diff --git a/src/northbridge/intel/e7520/Kconfig b/src/northbridge/intel/e7520/Kconfig
index 426db8b12f..ef2b7f65fe 100644
--- a/src/northbridge/intel/e7520/Kconfig
+++ b/src/northbridge/intel/e7520/Kconfig
@@ -1,3 +1,9 @@
config NORTHBRIDGE_INTEL_E7520
bool
+if NORTHBRIDGE_INTEL_E7520
+config DIMM_MAP_LOGICAL
+ hex
+ default 0x1248
+
+endif
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 235ce44f2b..6eed1964e9 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -1078,12 +1078,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Starting SDRAM Enable\n");
/* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
pci_write_config32(PCI_DEV(0, 0x00, 0), DRM,
- 0x00210000 | DIMM_MAP_LOGICAL);
-#else
- pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248);
-#endif
+ 0x00210000 | CONFIG_DIMM_MAP_LOGICAL);
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
diff --git a/src/northbridge/intel/e7525/Kconfig b/src/northbridge/intel/e7525/Kconfig
index d8bff2225b..04e3d8b619 100644
--- a/src/northbridge/intel/e7525/Kconfig
+++ b/src/northbridge/intel/e7525/Kconfig
@@ -1,3 +1,9 @@
config NORTHBRIDGE_INTEL_E7525
bool
+if NORTHBRIDGE_INTEL_E7525
+config DIMM_MAP_LOGICAL
+ hex
+ default 0x1248
+
+endif
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index b482bb9fec..aabe8cfba5 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -1055,12 +1055,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Starting SDRAM Enable\n");
/* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
pci_write_config32(ctrl->f0, DRM,
- 0x00210000 | DIMM_MAP_LOGICAL);
-#else
- pci_write_config32(ctrl->f0, DRM, 0x00211248);
-#endif
+ 0x00210000 | CONFIG_DIMM_MAP_LOGICAL);
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig
index a85162310e..079004bda9 100644
--- a/src/northbridge/intel/i3100/Kconfig
+++ b/src/northbridge/intel/i3100/Kconfig
@@ -1,3 +1,9 @@
config NORTHBRIDGE_INTEL_I3100
bool
+if NORTHBRIDGE_INTEL_I3100
+config DIMM_MAP_LOGICAL
+ hex
+ default 0x1248
+
+endif
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 5afddb7d9e..86e610feb3 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -973,12 +973,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Starting SDRAM Enable\n");
/* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
pci_write_config32(ctrl->f0, DRM,
- 0x00410000 | DIMM_MAP_LOGICAL);
-#else
- pci_write_config32(ctrl->f0, DRM, 0x00411248);
-#endif
+ 0x00410000 | CONFIG_DIMM_MAP_LOGICAL);
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {